Semiconductor device and manufacturing method thereof

ABSTRACT

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

TECHNICAL FIELD

The present invention relates to a semiconductor device including a transistor.

Note that the semiconductor device in this specification refers to any device that can function by utilizing semiconductor characteristics, and semiconductor elements and circuits, electro-optic devices including semiconductor elements and circuits, and electronic devices including semiconductor elements and circuits are all semiconductor devices.

BACKGROUND ART

In recent years, a technique by which transistors are formed using semiconductor thin films formed over a substrate having an insulating surface has been attracting attention. A transistor is used for a semiconductor device typified by a liquid crystal television. As a semiconductor thin film that can be applied to the transistors, a silicon-based semiconductor material is known, and an oxide semiconductor attracts attention as another material.

A transistor is manufactured mainly using a semiconductor material such as amorphous silicon or polycrystalline silicon. A transistor formed using amorphous silicon has low field-effect mobility, but such a transistor can be formed over a glass substrate with a larger area. On the other hand, a transistor formed using crystalline silicon has high field-effect mobility, but a crystallization step such as laser annealing is necessary and such a transistor is not always suitable for a larger glass substrate.

As a material of the oxide semiconductor, zinc oxide and a material containing zinc oxide as its component are known. Further, thin film transistors formed using an amorphous oxide (oxide semiconductor) having an electron carrier concentration of less than 10¹⁸/cm³ are disclosed (Patent Documents 1 to 3).

Moreover, there is a trend in an active matrix semiconductor device typified by a liquid crystal display device towards a larger screen, e.g., a 60-inch diagonal screen, and further, the development of an active matrix semiconductor device is aimed even at a screen size of a diagonal of 120 inches or more. In addition, a trend in resolution of a screen is toward higher definition, e.g., high-definition (HD) image quality (1366×768) or full high-definition (FHD) image quality (1920×1080), and prompt development of a so-called 4K Digital Cinema display device, which has a resolution of 3840×2048 or 4096×2160, is also pushed.

As a display device has a higher definition, the number of pixels needed for it is significantly increased. As a result, writing time for one pixel is shortened, and thus a transistor is required to have high speed operation characteristics, large on current, and the like. In the meantime, a problem of energy depletion in recent years has caused demand for a display device whose power consumption is suppressed. Therefore, a transistor is also required to have low off-state current and suppressed unnecessary leakage current.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2006-165527 -   [Patent Document 2] Japanese Published Patent Application No.     2006-165528 -   [Patent Document 3] Japanese Published Patent Application No.     2006-165529

DISCLOSURE OF INVENTION

A transistor using an oxide semiconductor has higher field-effect mobility than a transistor using amorphous silicon. However, a transistor using an oxide semiconductor has lower field-effect mobility than a transistor using polycrystalline silicon, so that field-effect mobility of a transistor using an oxide semiconductor is required to be further improved.

In addition, a difference from the stoichiometric composition in an oxide semiconductor arises in a formation process. For example, electrical conductivity of an oxide semiconductor is changed due to excess and deficiency of oxygen. Further, hydrogen that enters the oxide semiconductor thin film during the formation of the thin film forms an oxygen (O)-hydrogen (H) bond and serves as an electron donor, which is a factor of changing electric conductivity. Further, the O—H bond is a bond having polarity; and thus, the O—H bond might cause variation in characteristics of an active device such as a transistor formed using an oxide semiconductor.

Even when the electron carrier concentration is lower than 10¹⁸/cm³, the oxide semiconductor is substantially n-type, and the on/off ratio of the transistors disclosed in the above patent documents is only 10³. Such a low on/off ratio of the transistor is due to large off-state current.

The present invention is made in view of the foregoing technical background. Therefore, an object of the present invention is to provide a semiconductor device in which transistors with different characteristics, specifically, a transistor with excellent dynamic characteristics (on characteristics or frequency characteristics (referred to as f characteristics)) and a transistor having a reduced off-state current, are provided over one substrate. Further, another object is to provide a simple method for manufacturing the semiconductor device.

In order to achieve the above-described object, in the invention, an oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion is focused. A semiconductor from which an impurity which is to be an electron donor (donor) from an oxide semiconductor is removed and which has a larger energy gap than a silicon semiconductor can be used as a semiconductor which is intrinsic or substantially intrinsic. The electric characteristics of transistors is controlled by controlling the potential of a pair of conductive films which are provided on opposite sides form each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

One embodiment of the present invention is a semiconductor device in which a transistor with excellent dynamic characteristics and a transistor with stable electric characteristics (e.g., an extremely reduced off-state current) are used over one substrate. Specifically, an embodiment of the present invention is a semiconductor from which an impurity which is to be an electron donor (donor) from an oxide semiconductor is removed and which has a larger energy gap than a silicon semiconductor can be used. Using the oxide semiconductor, an oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is formed. In addition, a plurality of transistors having a structure in which conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween is provided over one substrate.

That is, an embodiment of the present invention is a semiconductor device including a first electrode layer, a first insulating film over the first electrode layer, an oxide semiconductor layer including a crystalline region in a surface portion of the oxide semiconductor layer, over the first insulating film, a second electrode layer and a third electrode layer over the first electrode layer and in contact with the oxide semiconductor layer, the second electrode layer having an end portion overlapping with the first electrode layer, and the third electrode layer having an end portion overlapping with the first electrode layer, a second insulating film including an oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer, and a fourth electrode layer overlapping with the first electrode layer and the oxide semiconductor layer, over the second insulating film. In addition, the semiconductor device includes a plurality of transistors in which an energy gap of an oxide semiconductor used in the oxide semiconductor layer is greater than or equal to 2 eV.

An embodiment of the present invention is an inverter circuit which includes the above-described semiconductor device including a depression transistor and an enhancement transistor.

An embodiment of the present invention is includes a display device which includes the above-described semiconductor device including a pixel portion and a driver circuit portion which drives the pixel portion.

An embodiment of the present invention is a driving method using the first electrode layer as a main gate electrode in at least one transistor and the fourth electrode layer as a main gate electrode in the other transistors in the above-described semiconductor device.

An embodiment of the present invention is a driving method using the fourth electrode layer as a main gate electrode in the depletion transistor and the fourth electrode layer as a main gate electrode in the enhancement transistor in the above-described inverter circuit.

An embodiment of the present invention is a driving method using the first electrode layer as a main gate electrode in at least one transistor included in the pixel portion and the fourth electrode layer as a main gate electrode in at least one transistor included in the driver circuit portion in the above-described display device.

An embodiment of the present invention is a manufacturing method of a semiconductor device including the steps of forming a first electrode layer, forming a first insulating film over the first electrode layer, forming an oxide semiconductor layer over the first insulating film, performing dehydration or dehydrogenation on the oxide semiconductor layer so that a crystalline region is formed in a surface portion of the oxide semiconductor layer, forming a second electrode layer and a third electrode layer over the first electrode layer and in contact with the oxide semiconductor layer, the second electrode layer having an end portion overlapping with the first electrode layer, and the third electrode layer having an end portion overlapping with the first electrode layer, forming a second insulating film including an oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer, and forming a fourth electrode layer overlapping with the first electrode layer and the oxide semiconductor layer, over the second insulating film. In addition, the above-described semiconductor device includes a plurality of transistors over one substrate in which an energy gap of an oxide semiconductor used in the oxide semiconductor layer is greater than or equal to 2 eV.

In this specification, an EL layer refers to a layer provided between a pair of electrodes in a light-emitting element. Thus, a light-emitting layer containing an organic compound that is a light-emitting substance which is interposed between electrodes is an embodiment of the EL layer.

Note that in this specification, a light-emitting device refers to an image display device, a light-emitting device, or a light source (including a lighting device). In addition, the light-emitting device includes any of the following modules in its category: a module in which a connector such as a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached to a light-emitting device; a module having a TAB tape or a TCP provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) directly mounted over a substrate over which a light-emitting element is formed by a chip on glass (COG) method.

According to one embodiment of the present invention, a crystalline region included in an oxide semiconductor layer is used as a channel formation region, whereby operation speed of the circuit included in a semiconductor device can be increased. In addition, a circuit is formed using a transistor in which a purified oxide semiconductor is used, whereby operation of the circuit included in a semiconductor device can be stabilized. Further, off-state current reduced to 1×10⁻¹³ A or lower, whereby a storage capacitor included in a semiconductor device can be reduced in size or in number. Further, a semiconductor device including transistors with different characteristics over one substrate can be provided. Furthermore, the semiconductor device can be manufactured by a simple method.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings;

FIGS. 1A to 1E each illustrate a manufacturing method of a semiconductor device according to an embodiment;

FIG. 2 illustrates a semiconductor device according to an embodiment;

FIGS. 3A to 3C each illustrate an inverter circuit according to an embodiment;

FIGS. 4A to 4C each illustrate a shift register according to an embodiment;

FIGS. 5A and 5B each illustrate a pulse output circuit according to an embodiment;

FIGS. 6A to 6D each illustrate a pulse output circuit according to an embodiment;

FIGS. 7A to 7D each illustrate a pulse output circuit according to an embodiment;

FIGS. 8A and 8B each illustrate a timing chart according to an embodiment;

FIGS. 9A and 9B are block diagrams of display devices according to an embodiment;

FIGS. 10A and 10B each illustrate a driver circuit of a display device according to an embodiment;

FIGS. 11A1 and 11A2 are cross-sectional views and FIG. 11B is a plan view each illustrating an embodiment of the present invention;

FIG. 12 is a cross-sectional view illustrating an embodiment of the present invention;

FIG. 13 is a cross-sectional view illustrating an embodiment of the present invention;

FIG. 14 shows an equivalent circuit of a pixel in a semiconductor device;

FIGS. 15A to 15C are cross-sectional views each illustrating an embodiment of the present invention;

FIGS. 16A and 16B are a cross-sectional view and a plan view, respectively, illustrating an embodiment of the present invention;

FIGS. 17A and 17B each illustrate an example of a usage mode of electronic paper;

FIG. 18 is an external view illustrating an example of an electronic book reader;

FIGS. 19A and 19B are external views illustrating examples of a television device and a digital photo frame, respectively;

FIGS. 20A and 20B are external views illustrating examples of game machines;

FIGS. 21A and 21B are external views illustrating examples of cellular phones;

FIGS. 22A1, 22A2, 22B1 and 22B2 are each illustrates an end portion of a display device according to an embodiment;

FIG. 23 is a longitudinal cross-sectional view of an inverted staggered transistor in which an oxide semiconductor is used;

FIG. 24A shows energy band diagrams (schematic diagrams) along the section A-A′ illustrated in FIG. 23 in the case in which the potential of the source and the potential of the drain are the same (V_(D)=0), and FIG. 24B shows energy band diagrams (schematic diagrams) along A-A′ illustrated in FIG. 23 in the case in which positive potential is applied to the drain (V_(D)>0) with respect to the source;

FIG. 25 shows an energy band diagram (a schematic diagram) along the section B-B′ illustrated in FIG. 23 in the case in which the gate voltage is 0 V;

FIG. 26A shows an energy band diagram (a schematic diagram) along B-B′ illustrated in FIG. 23 in the case in which a positive potential (V_(G)>0) is applied to a gate (GE1), and FIG. 26B shows an energy band diagram (a schematic diagram) along B-B′ illustrated in FIG. 23 in the case in which a negative potential (V_(G)<0) is applied to the gate (GE1); and

FIG. 27 shows a relation between the vacuum level and the work function of a metal (φM), and between the vacuum level and the electron affinity of an oxide semiconductor (χ).

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description below and it is easily understood by those skilled in the art that the mode and details can be changed variously. Therefore, the present invention is not construed as being limited to description of the embodiments. Note that in the drawings of this specification, the identical portions or portions having a similar function are denoted by the identical reference numerals, and description thereon may be omitted.

(Embodiment 1)

In this embodiment, one embodiment of a substrate provided with a circuit of a display device and a manufacturing method of the substrate provided with a circuit as one embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 1E.

FIG. 1E illustrates an example of a cross-sectional structure of a plurality of transistors formed over a substrate provided with a circuit of a display device. Transistors 440A and 440B illustrated in FIG. 1E each have a kind of four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween. Note that a so-called dual-gate transistor in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween is one embodiment of the four-terminal structure of this embodiment. Further, the case where the transistor 440B is applied to a pixel of a display device and the transistor 440A is applied to part of a driver circuit arranged in the periphery of a pixel portion will be described.

The transistor 440A includes a first electrode layer 421 a, a first insulating layer 402, an oxide semiconductor layer 404 a including a crystalline region 405 a, a second electrode layer 455 a, and a third electrode layer 455 b over a substrate 400 having an insulating surface. In addition, the transistor 440A includes a second insulating layer 428 which is in contact with the crystalline region 405 a and covers the transistor 440A, and a fourth electrode layer 422 a which is provided over a channel formation region with the second insulating layer 428 interposed therebetween. The first electrode layer 421 a and the oxide semiconductor layer 404 a including the crystalline region 405 a overlap with each other with the first insulating layer 402 interposed therebetween. Further, the second electrode layer 455 a and the third electrode layer 455 b are formed over the oxide semiconductor layer 404 a so that part of the second electrode layer 455 a part of the third electrode layer 455 b overlap with the oxide semiconductor layer 404 a.

The transistor 440B includes a first electrode layer 421 b, the first insulating layer 402, an oxide semiconductor layer 404 b including a crystalline region 405 b, a second electrode layer 455 c, and a third electrode layer 455 d over the substrate 400 having an insulating surface. In addition, the transistor 440B includes the second insulating layer 428 which is in contact with the crystalline region 405 b and covers the transistor 440B and a fourth electrode layer 422 b which is provided over the channel formation region with the second insulating layer 428 interposed therebetween. The first electrode layer 421 b and the oxide semiconductor layer 404 b including the crystalline region 405 b overlap with each other with the first insulating layer 402 interposed therebetween. Further, the second electrode layer 455 c and the third electrode layer 455 d are formed over the oxide semiconductor layer 404 b so that part of the second electrode layer 455 c part of the third electrode layer 455 d overlap with the oxide semiconductor layer 404 b.

The transistors 440A and 440B each have a dual-gate structure. In a transistor having a dual-gate structure, one or both of electrode layers which are provided on opposite sides from each other with respect to an oxide semiconductor layer, each with an insulating film arranged therebetween can be used as a gate electrode layer. Note that the second electrode layer and the third electrode layer function as a source electrode layer and a drain electrode layer.

In this embodiment, the fourth electrode layer 422 a of the transistor 440A is used as a main gate electrode of the transistor. Accordingly, a channel is formed in a region which is positioned between a region in contact with the second electrode layer 455 a of the oxide semiconductor layer 404 a and a region in contact with the third electrode layer 455 b of the oxide semiconductor layer 404 a, which is in contact with the second insulating layer 428, and which overlaps with the fourth electrode layer 422 a.

The first electrode layer and the fourth electrode layer are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with the insulating film arranged therebetween. Note that in this embodiment, in the case where the potential of the first electrode layer is higher that that of the fourth electrode layer, the first electrode layer is referred to as a main gate electrode, and in the case where the potential of the fourth electrode layer is higher that that of the first electrode layer, the fourth electrode layer is referred to as a main gate electrode. The potential of either the first electrode layer or the fourth electrode layer may be GND, 0 V, or in a floating state.

The first electrode layer 421 b of the transistor 440B is used as a main gate electrode of the transistor. Accordingly, a channel is formed in a region which is positioned between a region in contact with the second electrode layer 455 c of the oxide semiconductor layer 404 b and a region in contact with the third electrode layer 455 d of the oxide semiconductor layer 404 b, which is in contact with the first insulating layer 402, and which overlaps with the first electrode layer 421 b.

Note that the transistor 440B can have a light-transmitting property when the first electrode layer 421 b, the second electrode layer 455 c, the third electrode layer 455 b, and the fourth electrode layer 422 b are formed using a light-transmitting conductive film. In the case where a light-transmitting transistor is applied to a pixel of a display device, the aperture ratio of the pixel can be improved.

As a material of the light-transmitting conductive film, a conductive material that transmits visible light, for example, an In—Sn—O-based oxide conductive material, an In—Sn—Zn—O-based oxide conductive material, an In—Al—Zn—O-based oxide conductive material, an Sn—Ga—Zn—O-based oxide conductive material, an Al—Ga—Zn—O-based oxide conductive material, an Sn—Al—Zn—O-based oxide conductive material, an In—Zn—O-based oxide conductive material, an Sn—Zn—O-based oxide conductive material, an Al—Zn—O-based oxide conductive material, an In—O-based oxide conductive material, an Sn—O-based oxide conductive material, or a Zn—O-based oxide conductive material can be employed. In the case of using a sputtering method, deposition may be performed with a target including SiO₂ at greater than or equal to 2 wt % and less than or equal to 10 wt % so that the light-transmitting conductive film may include SiO_(x) (X>0) and be amorphous.

The first electrode layer 421 a, the second electrode layer 455 a, the third electrode layer 455 b, and the fourth electrode layer 422 a of the transistor 440A may be formed using a single-layer structure or a stacked structure including a film containing an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta as a main component. For the second electrode layer 455 a and the third electrode layer 455 b which are electrically connected to the oxide semiconductor layer, a material including metal with high oxygen affinity is preferably used.

As the oxide semiconductor layer, an In—Sn—Ga—Zn—O-based oxide semiconductor layer which is a four-component metal oxide; an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, or a Sn—Al—Zn—O-based oxide semiconductor layer which are three-component metal oxides; an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, a Zn—Mg—O-based oxide semiconductor layer, a Sn—Mg—O-based oxide semiconductor layer, or an In—Mg—O-based oxide semiconductor layer which are two-component metal oxides; or an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer which are one-component metal oxides can be used. Further, SiO₂ may be contained in the above oxide semiconductor layer.

As the oxide semiconductor layer, a thin film represented by InMO₃(ZnO)_(m) (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like. An oxide semiconductor layer whose composition formula is represented by InMO₃ (ZnO)_(m) (m>0), which includes Ga as M, is referred to as an In—Ga—Zn—O-based oxide semiconductor described above, and a thin film of the In—Ga—Zn—O oxide semiconductor is also referred to as an In—Ga—Zn—O-based film.

For the oxide semiconductor layer, the one which is subjected to dehydration or dehydrogenation at high temperature in a short time by a rapid thermal annealing (RTA) method or the like is used. This heating process makes a superficial portion of the oxide semiconductor layer have a crystalline region including so-called nanocrystals with a grain size of greater than or equal to 1 nm and less than or equal to 20 nm and the rest of the oxide semiconductor layer is amorphous or is formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals. Note that the above-described size of the nanocrystal is just an example, and the present invention is not construed as being limited to the above range.

In an oxide semiconductor layer having such a structure, a dense crystalline region including nanocrystals exists in its superficial portion. Therefore, in the case of using such an oxide semiconductor layer, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, can be prevented. As a result, deterioration of electric characteristics influenced by a change to an n-type, specifically increase in the off-state current can be prevented.

The crystalline region in the superficial portion of the oxide semiconductor layer includes crystal grains in which c-axes are oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer. For example, in the case of using an In—Ga—Zn—O-based oxide semiconductor material, the c-axes of the crystal grains of In₂Ga₂ZnO₇ in the crystalline region are oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. The crystalline region includes nanocrystals which are oriented in a predetermined direction. For example, in the case where an In—Ga—Zn—O-based oxide semiconductor material is used for the oxide semiconductor layer and nanocrystals are arranged so that c-axes of In₂Ga₂ZnO₇ are oriented in a direction substantially perpendicular to a substrate plane (or the surface of the oxide semiconductor layer), current flows in a b-axis direction (or an a-axis direction) of In₂Ga₂ZnO₇ in the transistor.

Note that the crystalline region may include a portion other than the crystal grains. The crystal structure of the crystal grains is not limited to the above structure, and the crystalline region may include crystal grains of another structure. For example, in the case of using an In—Ga—Zn—O-based oxide semiconductor material, crystal grains of InGaZnO₄ may be included in addition to the crystal grains of In₂Ga₂ZnO₇.

Hereinafter, a manufacturing process of the transistor 440A and the transistor 440B over one substrate is described with reference to FIGS. 1A to 1E.

First, a conductive film is formed over the substrate 400 having an insulating surface and a first photolithography step is performed thereon to form the first electrode layer 421 a and the first electrode layer 421 b. At this time, etching is preferably performed so that at least an end portion of the first electrode layer 421 a and the first electrode layer 421 b be tapered in order to prevent disconnection.

Note that a resist mask may be formed by an inkjet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced. Needless to say, an inkjet method can be applied not only to the first photolithography step but also to another photolithography step.

Note that as the substrate 400, any of the following substrates can be used: non-alkaline glass substrates formed using barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, and the like by a fusion method or a float method; ceramic substrates; plastic substrates having heat resistance enough to withstand a process temperature of this manufacturing process; and the like. Alternatively, a metal substrate such as a stainless steel alloy substrate which is provided with an insulating film over the surface may also be used.

Note that as the above glass substrate, a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a crystallized glass substrate or the like may be used.

The first electrode layer 421 a and the first electrode layer 421 b can be formed using a single layer or a stacked layer using any of the following: a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material which contains any of these materials as a main component; and a nitride containing any of these materials. Preferably, it is effective to form the first electrode layers with the use of a low-resistance metal material such as aluminum or copper, the low-resistance metal material is preferably used in combination with a refractory metal material because it has disadvantages such as low heat resistance and a tendency to be corroded. As the refractory metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like can be used.

At that time, a light-transmitting oxide conductive layer is used for part of the electrode layer and the wiring layer to increase the aperture ratio. For example, an oxide conductive layer including indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, or the like can be used for the light-transmitting conductive layer.

Further, the first electrode layer 421 a and the first electrode layer 421 b may be formed using different materials. For example, in order to improve the aperture ratio of a pixel portion, the first electrode layer 421 b can be formed using a light-transmitting conductive layer with respect to visible light, and in order to suppress wiring resistance, the first electrode layer 421 a in a driver circuit portion can be formed using a conductive film including metal as its main component, for example, a single film containing an element selected from titanium, molybdenum, tungsten, aluminum, chromium, copper, and tantalum as a main component or a stacked layer film including the film.

An insulating layer serving as a base film may be provided between the substrate 400 and the first electrode layers 421 a and 421 b. The base film has a function of preventing diffusion of an impurity element from the substrate 400, and can be formed to have a single-layer or stacked-layer structure including one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

Next, the first insulating layer 402 is formed over the first electrode layer 421 a and the first electrode layer 421 b. As the first insulating layer 402, a single-layer film or a stacked-layer film of any of silicon oxide layer, silicon oxynitride layer, silicon nitride oxide layer, silicon nitride layer, aluminum oxide layer, tantalum oxide layer, and the like can be used. The first insulating layer 402 is formed to a thickness greater than or equal to 50 nm and less than or equal to 250 nm with a CVD method, a sputtering method, or the like. Note that in the first insulating layer 402, an oxide insulating layer is provided preferably on the side where the first insulating layer 402 is in contact with the oxide semiconductor layer.

Note that the oxide semiconductor which becomes i-type or becomes substantially i-type (an oxide semiconductor which is purified) due to removal of an impurity is extremely sensitive to an interface state density or an interface electric charge; therefore, an interface with the insulating film is important. Accordingly, the insulating film which is in contact with the oxide semiconductor with high purity needs to be of high quality.

For example, high-density plasma CVD using microwaves (2.45 GHz) is preferable in that it produces a dense high-quality insulating film with high dielectric withstand voltage. This is because a close contact between an oxide semiconductor with high purity and a high-quality gate insulating film reduces interface state density and produces favorable interface characteristics.

In addition, since the insulating film formed using the high-density plasma CVD apparatus can have a uniform thickness, the insulating film has excellent step coverage. Further, the thickness of a thin insulating film formed with the high-density plasma CVD apparatus can be controlled precisely.

Needless to say, another method such as sputtering method or plasma CVD method can be employed as long as the method enables formation of a good-quality insulating film as a gate insulating film. Alternatively, an insulating film whose film quality and interface characteristics with the oxide semiconductor are improved by heat treatment performed after formation of the insulating film may be used. In any case, any insulating film that has a reduced interface state density with the oxide semiconductor and can form a favorable interface as well as having a favorable film quality as a gate insulating film can be used.

The first insulating layer 402 is formed using a high-density plasma CVD apparatus. Here, a high-density plasma CVD apparatus refers to an apparatus which can realize a plasma density higher than or equal to 1×10¹¹/cm³. For example, plasma is generated by applying a microwave power higher than or equal to 3 kW and lower than or equal to 6 kW so that the insulating film is formed.

A monosilane gas (SiH₄), nitrous oxide (N₂O), and a rare gas are introduced into a chamber as a source gas to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface, such as a glass substrate. After that, the supply of a monosilane gas may be stopped, and nitrous oxide (N₂O) and a rare gas may be introduced without exposure to the air to perform plasma treatment performed on a surface of the insulating film. The plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N₂O) and a rare gas is performed at least after the insulating film is formed. The insulating film formed through the above process procedure has a small thickness and is an insulating film whose reliability can be ensured even though it has a thickness less than 100 nm, for example.

In forming the first insulating layer 402, the flow ratio of a monosilane gas (SiH₄) to nitrous oxide (N₂O) which are introduced into the chamber is in the range of 1:10 to 1:200. In addition, as a rare gas which is introduced into the chamber, helium, argon, krypton, xenon, or the like can be used. In particular, argon, which is inexpensive, is preferably used.

In addition, since the insulating film formed by using the high-density plasma apparatus can have a uniform thickness, the insulating film has excellent step coverage. Further, with the high-density plasma apparatus, the thickness of a thin insulating film can be controlled precisely.

The insulating film formed through the above process procedure is greatly different from the insulating film formed using a conventional parallel plate PCVD apparatus. The etching rate of the insulating film formed through the above process procedure is lower than that of the insulating film formed using the conventional parallel plate PCVD apparatus by greater than or equal to 10% or greater than or equal to 20% in the case where the etching rates with the same etchant are compared to each other. Thus, it can be said that the insulating film formed using the high-density plasma apparatus is a dense film.

Alternatively, a silicon oxide layer formed by a CVD method using an organosilane gas can be used for the first insulating layer 402. As an organosilane gas, a silicon-containing compound such as tetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄), tetramethylsilane (TMS) (chemical formula: Si(CH₃)₄), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula: SiH(OC₂H₅)₃), or trisdimethylaminosilane (chemical formula: SiH(N(CH₃)₂)₃) can be used.

Alternatively, the first insulating layer 402 may be formed using one kind of oxide, nitride, oxynitride, and nitride oxide of aluminum, yttrium, or hafnium; or a compound including at least two or more kinds of the above.

Note that in this specification, oxynitride refers to a substance that contains more oxygen atoms than nitrogen atoms and nitride oxide refers to a substance that contains more nitrogen atoms than oxygen atoms. For example, a “silicon oxynitride film” means a film that contains oxygen atoms and nitrogen atoms so that the number of the oxygen atoms is larger than that of the nitrogen atoms and, in the case where measurements are performed using Rutherford backscattering spectrometry (RBS) and hydrogen forward scattering (HFS), contains oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 50 atomic % to 70 atomic %, 0.5 atomic % to 15 atomic %, 25 atomic % to 35 atomic %, and 0.1 atomic % to 10 atomic %, respectively. Further, a “silicon nitride oxide film” means a film that contains nitrogen atoms and oxygen atoms so that the number of the nitrogen atoms is larger than that of the oxygen atoms and, in the case where measurements are performed using RBS and HFS, contains oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 5 atomic % to 30 atomic %, 20 atomic % to 55 atomic %, 25 atomic % to 35 atomic %, and 10 atomic % to 30 atomic %, respectively. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above when the total number of atoms contained in the silicon oxynitride film or the silicon nitride oxide film is defined as 100 atomic %.

Next, over the first insulating layer 402, an oxide semiconductor film 403 is formed to a thickness greater than or equal to 5 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 20 nm (see FIG. 1A).

Note that before the oxide semiconductor film 403 is formed, dust on a surface of the first insulating layer 402 is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which, without application of voltage to a target side, an RF power source is used for application of voltage to a substrate side in an argon atmosphere to generate plasma in the vicinity of the substrate to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. After the reverse sputtering, the oxide semiconductor film is formed without being exposed to air, whereby dust or moisture can be prevented from attaching to an interface between the first insulating layer 402 and the oxide semiconductor film 403.

As the oxide semiconductor film, an In—Sn—Ga—Zn—O-based oxide semiconductor layer which is a four-component metal oxide described above; an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, or a Sn—Al—Zn—O-based oxide semiconductor layer which are three-component metal oxides described above; an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, a Zn—Mg—O-based oxide semiconductor layer, a Sn—Mg—O-based oxide semiconductor layer, or an In—Mg—O-based oxide semiconductor layer which are two-component metal oxides described above; or an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer which are one-component metal oxides described above can be used. Further, SiO₂ may be contained in the above oxide semiconductor film. As an oxide semiconductor film, an above-described thin film expressed by InMO₃(ZnO)_(m) (m>0) can be used.

The oxide semiconductor film can be formed with a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. In the case of using a sputtering method, film deposition may be performed using a target containing SiO₂ at greater than or equal to 2 percent by weight and less than or equal to 10 percent by weight and SiOx (x>0) which inhibits crystallization may be contained in the oxide semiconductor film.

Here, film formation is performed using a target for forming an oxide semiconductor including In, Ga, and Zn (the composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [mol ratio] or In₂O₃:Ga₂O₃:ZnO=1:1:2 [mol ratio]) under the following conditions: the distance between a substrate and a target is 100 mm, the pressure is 0.6 Pa, the direct-current (DC) power supply is 0.5 kW, and the atmosphere is oxygen (the flow rate of oxygen is 100%). Note that a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness distribution can be uniform. In this embodiment, as the oxide semiconductor film, an In—Ga—Zn—O-based film having a thickness of 15 nm is formed with a sputtering method using a target for forming an In—Ga—Zn—O-based oxide semiconductor.

In that case, the oxide semiconductor film is preferably formed while moisture remaining in the treatment chamber is removed. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

In addition, it is preferable that the oxide semiconductor film be successively formed over the first insulating layer 402. The multi-chamber sputtering apparatus used here is provided with the target of silicon or silicon oxide (artificial quarts), and the target for formation of an oxide semiconductor film. The deposition chamber provided with the target for formation of an oxide semiconductor film is also provided with at least a cryopump as an evacuation unit. Note that a turbo molecular pump may be used instead of the cryopump, and a cold trap may be provided above an inlet of the turbo molecular pump so that moisture or the like may be adsorbed.

From the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom such as H₂O, a carbon atom, a compound containing a carbon atom, and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such as hydrogen, water, a hydroxyl group, or hydride is reduced to approximately the ppm level or the ppb level be used as the sputtering gas for the deposition of the oxide semiconductor film.

The oxide semiconductor film may be formed in the state where the substrate is heated. At that time, the substrate is heated higher than or equal to 100° C. and lower than or equal to 600° C., preferably, higher than or equal to 200° C. and lower than or equal to 400° C. By heating the substrate during deposition, the impurity concentration in the oxide semiconductor film can be reduced.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a direct-current power source is used, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case of forming an insulating film, and a DC sputtering method is mainly used in the case of forming a metal conductive film.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for magnetron sputtering, and a sputtering apparatus used for ECR sputtering in which plasma generated with the use of microwaves is used without using glow discharge.

Furthermore, as a deposition method by sputtering, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during deposition.

Next, through a second photolithography step, a resist mask is formed. Then, the In—Ga—Zn—O-based film is etched. In etching, organic acid such as citric acid or oxalic acid can be used for etchant. Etching is performed so that the end portions of the oxide semiconductor layers 404 a and 404 b have tapered shapes, breakage of a wiring due to a step shape can be prevented. Note that etching here is not limited to wet etching and dry etching may also be used.

Next, dehydration or dehydrogenation of the oxide semiconductor layers 404 a and 404 b is performed. First heat treatment for the dehydration or dehydrogenation can be performed with the use of resistance heating method, lamp irradiation, or the like in an inert gas atmosphere through rapid thermal annealing (RTA) treatment at a temperature higher than or equal to 500° C. and lower than or equal to 750° C. (or a temperature lower than or equal to the strain point of a glass substrate) for approximately one minute to ten minutes, preferably at 650° C. for approximately greater than or equal to three minutes and less than or equal to six minutes. With an RTA method, dehydration or dehydrogenation can be performed in a short time; therefore, treatment can be performed even at a temperature higher than the strain point of a glass substrate. Note that the timing of heat treatment is not limited to this timing and may be performed plural times, for example, before and after a photolithography step or a deposition step.

Note that in this specification, heat treatment in the atmosphere of an inert gas such as nitrogen or a rare gas is referred to as heat treatment for dehydration or dehydrogenation. In this specification, dehydrogenation does not refer to only elimination in the form of H₂ by the heat treatment, and dehydration or dehydrogenation also refers to elimination of H, OH, and the like for convenience.

It is important that the temperature is decreased from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated to room temperature in the same furnace used for the dehydration or dehydrogenation with the oxide semiconductor layer prevented from being exposed to air so that entry of water or hydrogen into the oxide semiconductor layer is prevented. When a transistor is formed using an i-type oxide semiconductor layer which is obtained by changing an oxide semiconductor layer into a low-resistance oxide semiconductor layer in an oxygen-deficient state, i.e., an n-type (e.g., n⁻-type or n⁺-type) oxide semiconductor layer through dehydration or dehydrogenation and by changing the low-resistance oxide semiconductor layer into a high-resistance oxide semiconductor layer through supply of oxygen, the threshold voltage of the transistor can be positive, so that a switching element having so-called normally-off characteristics can be realized. It is preferable that a channel in a transistor of a display device be formed at a positive threshold voltage which is as close to 0 V as possible. If the threshold voltage of the transistor is negative, it tends to be normally on; in other words, current flows between the source electrode and the drain electrode even when the gate voltage is 0 V. In an active matrix display device, electric characteristics of a transistor included in a circuit are important and the performance of the display device depends on the electrical characteristics. In particular, of the electric characteristics of the transistor, the threshold voltage (V_(th)) is important. When the threshold voltage value is high or is on the minus side even when the field effect mobility is high, it is difficult to control the circuit. In the case where a transistor has high threshold voltage, the transistor cannot perform a switching function as a transistor and might be a load when a transistor is driven at low voltage. In the case of an n-channel transistor, it is desirable that only after a positive voltage is applied as a gate voltage, a channel be formed and a drain current flows. A transistor in which a channel is not formed unless driving voltage is raised and a transistor in which a channel is formed and drain current flows even when negative voltage is applied are unsuitable for a transistor used in a circuit.

In addition, when the temperature is decreased from the heating temperature T, the gas atmosphere may be switched to a gas atmosphere which is different from that used when the temperature is raised to the heating temperature T. For example, cooling is performed by using the same furnace that is used for the dehydration or dehydrogenation and by filling the furnace with a high-purity oxygen gas, a high-purity N₂O gas, or ultra-dry air (having a dew point of −40° C. or lower, preferably −60° C. or lower) without exposure to the air.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not contained in the atmosphere. Alternatively, the purity of an inert gas which is introduced into a heat treatment apparatus is preferably 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

In the case where heat treatment is performed under an inert gas atmosphere, an oxide semiconductor layer is changed into an oxygen-deficient oxide semiconductor layer by the heat treatment to be a low-resistant oxide semiconductor layer, i.e. an n-type (e.g., n⁻-type) oxide semiconductor layer. After that, oxygen is supplied to an oxygen-deficient portion of the oxide semiconductor layer by the formation of an oxide insulating layer which is in contact with the oxide semiconductor layer. Thus, the oxide semiconductor layer is made to be i-type; that is, the oxide semiconductor layer is changed into a high-resistance oxide semiconductor layer. Accordingly, it is possible to form a highly reliable transistor having favorable electric characteristics.

In the oxide semiconductor layer which is sufficiently dehydrated or dehydrogenated under the above conditions, at least a peak at around higher than or equal to 250° C. and lower than or equal to 300° C. of two peaks in spectra which show discharge of moisture is not detected with thermal desorption spectroscopy (TDS) even when the temperature of the dehydrated or dehydrogenated oxide semiconductor layer is increased to 450° C.

Note that the oxide semiconductor layer 404 a and the oxide semiconductor layer 404 b are each an amorphous layer having many dangling bonds at the stage where the oxide semiconductor layers 404 a and 404 b are in an as-depo state. Through a first heating step for the dehydration or dehydrogenation, dangling bonds that exist close to each other are bonded, so that the oxide semiconductor layers 404 a and 404 b can have an ordered amorphous structure. When the ordering proceeds, the oxide semiconductor layers 404 a and 404 b are formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals, or are formed of amorphousness. The crystalline region 405 a and the crystalline region 405 b including nanocrystals are formed in the superficial portion of the oxide semiconductor layer 404 a and the oxide semiconductor layer 404 b (FIG. 1B). The rest of the oxide semiconductor layer 404 a and the oxide semiconductor layer 404 b come to be amorphous or be formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals. Note that the crystalline region 405 a and the crystalline region 405 b are part of the oxide semiconductor layer 404 a and the oxide semiconductor layer 404 b respectively, and hereinafter, the “the oxide semiconductor layer 404 a” and “the oxide semiconductor layer 404 b” includes the crystalline region 405 a and the crystalline region 405 b, respectively. Here, the microcrystal is a so-called nanocrystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm, which is smaller than that of a microcrystalline particle generally called a microcrystal.

In the crystalline regions 405 a and 405 b, a nanocrystal which is c-axis-oriented in a direction perpendicular to a surface of the layer is preferably formed. In that case, it is preferable that the long axis of the crystal is in the c-axis direction and the size in the short-axis direction is greater or equal to 1 nm and less or equal to 20 nm.

Note that, the crystalline region is not formed in a side surface portion of the oxide semiconductor layer depending on the order of steps, and in such a case, the crystalline region is formed only in a superficial portion, except for the side surface portion. However, the area of the side surface portion is small, and the effect of suppressing the deterioration of electric characteristics or improving the dielectric withstand voltage can be maintained in that case as well.

Further, the first electrode layer 421 a and the first electrode layer 421 b are crystallized to be microcrystalline layers or polycrystalline layers in some cases, depending on the condition of the first heat treatment or a material of the first electrode layers 421 a and 421 b. For example, in the case where an indium tin oxide is used for a material of the first electrode layers 421 a and 421 b, they are crystallized by the first heat treatment at 450° C. for one hour, whereas in the case where an indium tin oxide containing a silicon oxide is used as the first electrode layers 421 a and 421 b, they are not easily crystallized.

The oxide semiconductor layers 404 a and 404 b after the first heat treatment are oxygen-deficient oxide semiconductor layers, and the carrier concentration is higher than the carrier concentration right after the deposition and preferably 1×10¹⁸/cm³ or more. Thus the oxide semiconductor layers 404 a and 404 b have lower resistance.

The first heat treatment for the oxide semiconductor layers can be performed before the oxide semiconductor film is processed into the island-shaped oxide semiconductor layers. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and subjected to a photolithography step to form the island-shaped oxide semiconductor layers.

Then, although not illustrated, an opening (also referred to as a contact hole) for connecting the first electrode layer to the source electrode layer or the drain electrode layer which will be described later is formed in the first insulating layer 402. The contact hole is formed by forming a mask over the first insulating layer 402 by a photolithography method, an inkjet method, or the like, and then selectively etching the first insulating layer 402 using the mask. Note that the contact hole may be formed after the formation of the first insulating layer 402 and before the formation of the oxide semiconductor film 403.

Next, a conductive film which to be as a source electrode and a drain electrode (including wires formed in the same layer as the source electrode and the drain electrode) is formed over the oxide semiconductor layers 404 a and 404 b. The conductive film is formed with a thickness greater than or equal to 100 and less than or equal to 500 nm, preferably greater than or equal to 200 and less than or equal to 300 nm.

The source electrode and the drain electrode are formed using a metal material such as Al, Cu, Cr, Ta, Ti, Mo, or W, or an alloy material containing any of these metal materials as its component. A structure may be employed in which a high-melting-point metal layer of Cr, Ta, Ti, Mo, W, or the like is stacked over one side or both sides of a metal layer of Al, Cu, or the like. Heat resistance can be increased by using an Al material into which an element such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc or Y which prevents the generation of hillocks or whiskers on the Al film is added.

The source electrode and the drain electrode (including wires formed in the same layer as the source electrode and the drain electrode) may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), an indium oxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO), indium oxide and zinc oxide (In₂O₃—ZnO), or a material which is added silicon or silicon oxide to the metal oxide material can be used. The metal conductive film is not limited to a single layer containing the above-described element and may be two or more layers. However, a material of the conductive film preferably has heat resistance that can withstand at least second heat treatment performed later.

For the conductive film which is in contact with the oxide semiconductor layers 404 a and 404 b, a material including metal with high oxygen affinity is preferable. As the metal with high oxygen affinity, one or more materials selected from titanium (Ti), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and thorium (Th) are preferable. In this embodiment, a titanium film is used.

When the oxide semiconductor layer and the conductive film with high oxygen affinity are formed in contact with each other, the carrier density in the vicinity of the interface is increased and a low-resistance region is formed, whereby the contact resistance between the oxide semiconductor layer and the conductive film can be reduced. This is because the conductive film with high oxygen affinity extracts oxygen from the oxide semiconductor layer and thus either or both a layer which includes metal in the oxide semiconductor layer in excess (such a layer is referred to as a composite layer) and an oxidized conductive film are formed in the interface between the oxide semiconductor layer and the conductive film. For example, in a structure where an In—Ga—Zn—O-based oxide semiconductor layer is in contact with a titanium film, an indium-excess layer and a titanium oxide layer are formed in the vicinity of the interface where the oxide semiconductor layer is in contact with the titanium film in some cases. In other cases, either one of the indium-excess layer and the titanium oxide layer is formed in the vicinity of the interface where the oxide semiconductor layer is in contact with the titanium film. The indium-excess layer which is an oxygen-deficient In—Ga—Zn—O-based oxide semiconductor layer has high electric conductivity; therefore, the contact resistance between the oxide semiconductor layer and the conductive film can be reduced.

Note that a titanium film or a titanium oxide film having conductivity may be used as the conductive film which is in contact with the oxide semiconductor layer. In that case, in the structure where the In—Ga—Zn—O-based oxide semiconductor layer is in contact with the titanium oxide film, an indium-excess layer might be formed in the vicinity of the interface where the oxide semiconductor layer is in contact with the titanium oxide film.

For the conductive film, a conductive material having a light-transmitting property with respect to visible light can be used. As the conductive material having a light-transmitting property with respect to visible light, a transparent conductive oxide including any of indium, tin, or zinc is preferable. For example, indium oxide (In₂O₃) or an indium oxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO) can be used. Alternatively, a transparent conductive oxide to which an insulating oxide such as silicon oxide is added may be used. When a transparent conductive oxide is used for the conductive film, the aperture ratio of the display device can be improved.

As a formation method of the conductive film, an arc discharge ion plating method or a spray method may be employed. Alternatively, the conductive film may be formed by discharging a conductive nanopaste of silver, gold, copper, or the like by a screen printing method, an ink-jet method, or the like and baking the nanopaste.

Then, a mask is formed over the conductive film by a photolithography method, an inkjet method, or the like and the conductive film is etched using the mask; thus, the source electrode and the drain electrode are formed (FIG. 1C). In this embodiment, a 200-nm-thick Ti film is formed by a sputtering method as the conductive film, and the conductive film is selectively etched by a wet etching method or a dry etching method using a resist mask, whereby the second electrode layer 455 a, the third electrode layer 455 b, the second electrode layer 455 c, and the third electrode layer 455 d which function as the source electrodes and the drain electrodes are formed.

Next, the second insulating layer 428 which covers the second electrode layer 455 a, the third electrode layer 455 b, the second electrode layer 455 c, the third electrode layer 455 d, and the exposed parts of the oxide semiconductor layers 404 a and 404 b is formed (FIG. 1D). The thickness of the second insulating layer 428 is preferably greater than or equal to 50 nm and less than or equal to 250 nm. The second insulating layer 428 includes an oxide insulating layer on the side where the second insulating layer 428 is in contact with the oxide semiconductor layer. As the oxide insulating layer in contact with the oxide semiconductor layer of the second insulating layer 428, an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, a tantalum oxide layer, a yttrium oxide layer, or a hafnium oxide layer is can be used.

The oxide insulating layer can be formed as appropriate with a sputtering method or the like, i.e. a method with which impurities such as moisture or hydrogen are not mixed into the oxide insulating layer. In this embodiment, a silicon oxide film is formed as the oxide insulating layer by a sputtering method. The substrate temperature in the deposition may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, the substrate temperature in film formation is 100° C. In order to prevent entry of an impurity such as water or hydrogen in the deposition, it is preferable to perform pre-baking under reduced pressure at a temperature higher than or equal to 150° C. and lower than or equal to 350° C. for greater than or equal to two minutes and less than or equal to ten minutes before the deposition, and to form an oxide insulating layer without exposure to the air. The silicon oxide film can be formed by a sputtering method under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically, argon) and oxygen. As a target, a silicon oxide target or a silicon target may be used. For example, with the use of a silicon target, a silicon oxide film can be formed by a sputtering method in an atmosphere of oxygen and a rare gas. During the formation of the oxide insulating layer in contact with the oxide semiconductor layer whose resistance is reduced, impurities such as moisture, a hydrogen ion, and OH⁻ are prevented from entering the oxide insulating layer.

A structure in which an inorganic insulating film is stacked over the oxide insulating layer so as to block entry of impurities such as moisture, a hydrogen ion, OH⁻ to the oxide semiconductor layer from the outside is preferable. As the inorganic insulating film stacked over the oxide insulating layer of the second insulating layer 428, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, or the like can be used.

In this embodiment, deposition is performed by a pulsed DC sputtering method with the use of a columnar polycrystalline, boron-doped silicon target having a purity of 6N (with a resistivity of 0.01 Ω·cm) under conditions where the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, the direct current (DC) power is 6 kW, and the atmosphere is an oxygen atmosphere (the proportion of the oxygen flow is 100%). The film thickness is 300 nm. It is preferable that a high-purity gas in which an impurity such as hydrogen, water, a hydroxyl group, or hydride is reduced to approximately the ppm level or the ppb level be used as the sputtering gas for the deposition of the second insulating layer 428.

Next, second heat treatment is performed in an inert-gas atmosphere or a nitrogen atmosphere (preferably at a temperature higher than or equal to 200° C. and lower than or equal to 400° C., e.g., higher than or equal to 250° C. and lower than or equal to 350° C.). For example, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. Alternatively, RTA treatment may be performed at high temperature for a short time as in the first heat treatment. In the second heat treatment, since the oxide insulating layer is heated in contact with the oxide semiconductor layer, oxygen is supplied to the oxygen-deficient portion of the oxide semiconductor layer whose resistance is reduced by the first heat treatment, and thus the oxide semiconductor layer can be changed into a high-resistance oxide semiconductor layer (an i-type oxide semiconductor layer).

In this embodiment, the second heat treatment is performed after formation of the silicon oxide film; however, the timing of the heat treatment is not limited to the timing immediately after formation of the silicon oxide film as long as it is after deposition of the silicon oxide film.

Then, a photolithography step is performed to form a resist mask, and the second insulating layer 428 is etched to form a contact hole which reaches the second electrode layer 455 d.

Next, after a conductive film is formed over the second insulating layer 428, the fourth electrode layer 422 a, the fourth electrode layer 422 b, and a connection electrode layer 422 c which is connected to a pixel electrode layer later are formed by a photolithography step performed on the conductive film (FIG. 1E). As the conductive film, a single-layer structure or a stacked-layer structure including a film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as a main component can be used. Note that in the case where the third electrode layer 455 d and the pixel electrode layer are directly connected, the connection electrode layer 422 c may be omitted.

In this embodiment, the fourth electrode layer 422 a of the transistor 440A is used as a main gate electrode of the transistor. The potential of the first electrode layer 421 a may be less than or equal to that of the fourth electrode layer 422 a, GND, or 0 V, or the first electrode layer 421 a may be in a floating state.

In addition, the first electrode layer 421 b of the transistor 440B is used as a main gate electrode of the transistor. The potential of the fourth electrode layer 422 b may be less than or equal to that of the first electrode layer 421 b, GND, or 0 V, or the fourth electrode layer 422 b may be in a floating state.

Each of the transistors has the four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween, and thus the reliability of the transistors can be improved. Specifically, in a bias-temperature stress test (hereinafter, referred to as a BT test) for examining reliability of a transistor, the amount of change in threshold voltage of the thin film transistor between before and after the BT test can be reduced.

Note that as illustrated in FIG. 2, a structure in which the transistor which is used the first electrode layer is used as a main gate electrode is not provided with the fourth electrode layer may be employed.

In FIG. 2, an example of a cross-sectional structure of a plurality of transistors formed over a substrate with a circuit of a display device is illustrated. The transistor 440A illustrated in FIG. 2 has a kind of four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween, and a transistor 450 is an inverted staggered transistor.

Note that the transistor 440A is preferably formed in a part of the driver circuit arranged in a periphery of the pixel portion of the display device, and the transistor 450 is preferably formed in part of the pixel circuit or the driver circuit or in the protective circuit.

The transistor 450 includes a first electrode layer 421 c, the first insulating layer 402, an oxide semiconductor layer 404 c including the crystalline region 405 c, a second electrode layer 455 e, and a third electrode layer 455 f over the substrate 400 having an insulating surface. In addition, the transistor 450 includes the second insulating layer 428 which is in contact with a crystalline region 405 c and covers the transistor 450.

The oxide semiconductor layer 404 c overlaps with the first electrode layer 421 c with the first insulating layer 402 provided therebetween. Further, the second electrode layer 455 e and the third electrode layer 455 f are formed over the oxide semiconductor layer 404 c so that part of the second electrode layer 455 e part of the third electrode layer 455 f overlap with the oxide semiconductor layer 404 c.

Note that a protective insulating layer may be formed so as to cover the transistors 440A and 450B. The protective insulating layer is formed using a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or the like.

In the pixel portion, a planarization insulating layer may be formed over the fourth electrode layer 422 b. The planarization insulating layer can be formed of a heat-resistant organic material, such as an acrylic resin, polyimide, a benzocyclobutene-based resin, polyamide, or an epoxy resin. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the planarization insulating layer may be formed by stacking a plurality of insulating films formed of these materials. Further, a color filter layer may be used as a planarization insulating layer.

A storage capacitor in which the first insulating layer 402 or a dielectric layer including an oxide insulating layer is arranged between a capacitor wiring which can be formed using the same material by the same step as the first electrode layer 421 b and a capacitor electrode which can be formed using the same material by the same step as the fourth electrode layer 422 b may be formed over the same substrate. The transistor 440B and pixels including the storage capacitor are arranged in matrix so that a pixel portion is formed and the substrate in which the driver circuit including the transistor 440A is arranged in the periphery of the pixel portion can be one substrate used to manufacture an active matrix display device.

Further, in the case where a display device is manufactured by using the transistors 440A and 440B, a power source supply line which is electrically connected to the source electrode layer of the transistor is provided. The power source supply line intersects with a gate wiring and is formed using the same material by the same step as the connection electrode layer 422 c formed using a conductive film. Alternatively, the power source supply line intersects with a source wiring and is formed using the same material by the same step as the first electrode layer 421 b.

Furthermore, in the case where a light-emitting device is manufactured, one electrode of the light-emitting element is electrically connected to the source electrode layer or the drain electrode layer of the driving transistor, and a common potential line which is electrically connected to the other electrode of the light-emitting element is provided. Note that the common potential line is formed using the same material and through the same process as the connection electrode layer 422 c formed using a metal conductive film. Alternatively, the common potential line is formed using the same material by the same step as the first electrode layer 421 b.

The transistor including the oxide semiconductor layer whose concentration of hydrogen is reduced through the above-described process has a characteristic of extremely small off-state current, which is 1×10⁻¹³ A or less. As a transistor with small off-state current, for example, there is a transistor using silicon carbide (e.g., 4H—SiC). There are some commonalities between an oxide semiconductor and 4H—SiC. The carrier concentration is one example of the commonalities between the oxide semiconductor and 4H—SiC. In accordance with Fermi-Dirac distribution at room temperature, the minority carrier density in an oxide semiconductor is estimated to be approximately 10⁻⁷/cm³. This value of the minority carrier density is extremely small similarly to that in 4H—SiC, which is 6.7×10⁻¹¹/cm³. When the minority carrier density of an oxide semiconductor is compared with the intrinsic carrier density of silicon (approximately 1.4×10¹⁰/cm³), it can be understood well that the minority carrier density of an oxide semiconductor is significantly low. In addition, the energy band gap of the oxide semiconductor is greater than or equal to 3.0 eV and less than or equal to 3.5 eV, and the energy band gap of 4H—SiC is 3.26 eV. Therefore, an oxide semiconductor has in common with silicon carbide in being a wide band-gap semiconductor.

On the other hand, there is a major difference between an oxide semiconductor and silicon carbide, that is, the process temperature. In general, a semiconductor process using silicon carbide includes a heat treatment for activation at higher than or equal to 1500° C. and lower than or equal to 2000° C. At such a high temperature, a semiconductor substrate, a semiconductor element, or the like using a semiconductor material other than silicon carbide is damaged, and thus, it is difficult to form a semiconductor element using silicon carbide over an integrated circuit using a semiconductor material other than silicon carbide. On the other hand, an oxide semiconductor can be deposited through heat treatment at higher than or equal to 300° C. and lower than or equal to 500° C. (at a temperature lower than or equal to the glass transition temperature, approximately 700° C. at a maximum). Therefore, it is possible to form a semiconductor element using an oxide semiconductor after forming an integrated circuit using another semiconductor material.

In the case of using an oxide semiconductor, there is an advantage that it is possible to use a substrate having low heat resistance such as a glass substrate, which is different from the case where silicon carbide is used. Moreover, an oxide semiconductor can be deposited without heat treatment at high temperature so that energy cost can be reduced sufficiently as compared with the case of using silicon carbide.

Note that a lot of research is done on properties of an oxide semiconductor such as DOS (density of states); however, the research does not include an idea that DOS itself is reduced sufficiently. In one embodiment of the present invention, water and hydrogen having possibility of affecting the DOS in the energy band gap are eliminated from an oxide semiconductor, so that a purified oxide semiconductor is formed. This idea is based on the idea that the DOS itself is reduced sufficiently. Therefore, manufacture of industrial products with extremely high quality can be realized.

Furthermore, oxygen may be supplied to a metal dangling bond generated by oxygen deficiency so as to reduce the DOS due to oxygen defect, whereby more purified (i-type)oxide semiconductor can be formed. For example, an oxide film having an excessive amount of oxygen may be formed in close contact with a channel formation region, and oxygen may be supplied from the oxide film so that DOS due to the oxygen defect can be reduced.

It is said that the defect of an oxide semiconductor is due to the level under the conduction band greater than or equal to 0.1 eV and less than or equal to 0.2 eV caused by an excessive amount of halogen, deep level caused by oxygen vacancy, or the like. Therefore, the technical idea of removing hydrogen completely and supplying oxygen sufficiently in order to eliminate those defects would be reasonable.

In general, an oxide semiconductor is an n-type semiconductor; however, in one embodiment of the present invention, an impurity especially water or hydrogen is removed so that an i-type oxide semiconductor is obtained. In this respect, it can be said that one embodiment of the disclosed invention includes a novel technical idea because it is different from an i-type semiconductor such as silicon added with an impurity.

A transistor using an oxide semiconductor has some characteristics. Here, the conduction mechanism of the oxide semiconductor is explained with reference to FIG. 23, FIGS. 24A and 24B, FIG. 25, and FIGS. 26A and 26B. Note that the following description is just a consideration and does not deny the validity of the invention.

FIG. 23 is a cross-sectional view of an inverted staggered transistor which includes an oxide semiconductor. An oxide semiconductor layer (OS) is provided over a gate electrode (GE1) with a gate insulating film (GI) provided therebetween, and a source electrode (S) and a drain electrode (D) are provided over the oxide semiconductor layer. Furthermore, a back gate (GE2) is provided over the source electrode and the drain electrode with an insulating layer provided therebetween.

FIGS. 24A and 24B are energy band diagrams (schematic diagrams) along the section A-A′ illustrated in FIG. 23. FIG. 24A illustrates the case where the voltage between the source and the drain is zero (V_(D)=0 V, the potential of the source and the potential of the drain are the same). FIG. 24B illustrates a case where positive potential with respect to the source is applied to the drain (V_(D)>0).

FIG. 25 and FIGS. 26A and 26B are energy band diagrams (schematic diagrams) along the section B-B′ in FIG. 23. FIG. 25 shows the case where the gate voltage is 0 V. FIG. 26A shows a state where a positive potential (V_(G)>0) is applied to the gate (GE1), that is, a case where the transistor is in an on-state where carriers (electrons) flow between the source and the drain. FIG. 26B shows a state where a negative potential (V_(G)<0) is applied to the gate (GE1), that is, a case where the transistor is in an off state (where minority carriers do not flow). In the state where the oxide semiconductor has a thickness of approximately 50 nm and the donor concentration in the purified oxide semiconductor is lower than or equal to 1×10¹⁸/cm³, a depletion layer expands to the entire oxide semiconductor in the off state. That is, the transistor can be regarded as a complete depletion transistor.

FIG. 27 shows a relation between the vacuum level and the work function of a metal (φ_(M)) and a relation between the vacuum level and the electron affinity of an oxide semiconductor (χ).

A metal is degenerated, so that the Fermi level is located in the conduction band. In contrast, a conventional oxide semiconductor is of n-type, and the Fermi level (E_(f)) in that case is located closer to the conduction band and is away from the intrinsic Fermi level (E_(i)) that is located in the middle of the band gap. Note that it is known that part of hydrogen contained in the oxide semiconductor forms a donor and might be a factor that causes an oxide semiconductor to change into an n-type oxide semiconductor.

On the other hand, an oxide semiconductor of the present invention is an intrinsic (i-type) or a substantially intrinsic oxide semiconductor which is obtained in such a manner that an oxide semiconductor is purified so that an impurity other than main components of the oxide semiconductor is prevented from being contained therein as much as possible by removing hydrogen that is an n-type impurity from the oxide semiconductor. In other words, a feature is that a purified i-type (intrinsic) semiconductor, or a semiconductor close thereto, is obtained not by adding an impurity but by removing an impurity such as hydrogen or water as much as possible. This enables the Fermi level (E_(f)) to be at the same level as the intrinsic Fermi level (E_(i)).

It is said that in the case where the band gap (E_(g)) of the oxide semiconductor is 3.15 eV, electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) used for forming the source and drain electrodes is substantially equal to the electron affinity (χ) of the oxide semiconductor. In that case, a Schottky barrier for electrons is not formed at an interface between the metal and the oxide semiconductor.

In other words, in the case where the work function of metal (φM) and the electron affinity (χ) of the oxide semiconductor are equal to each other and the metal and the oxide semiconductor are in contact with each other, an energy band diagram (a schematic diagram) as illustrated in FIG. 24A is obtained.

In FIG. 24B, black circles (●) represent electrons. A dashed line indicates movement of electrons when a voltage is not applied to a gate (V_(G)=0) in the state where a positive voltage is given to a drain (V_(D)>0), and a solid line indicates movement of electrons when a positive voltage is applied to a gate (V_(G)>0) in the state where a positive voltage is given to a drain (V_(D)>0). In the case where a positive voltage is applied to the gate (V_(G)>0), on application of a positive potential to the drain, the electron is injected into the oxide semiconductor over the barrier (h) and flows toward the drain. In that case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage; in the case where a positive voltage is applied to the gate (V_(G)>0) and a positive drain voltage is applied, the height of the barrier (h) is smaller than the height of the barrier in FIG. 24A where no voltage is applied, i.e., ½ of the band gap (E_(g)). In the case where a voltage is not applied to the gate, a carrier (electron) is not injected to the oxide semiconductor side from an electrode because of high potential barrier, so that a current does not flow, which means an off state. On the other hand, when positive voltage is applied to the gate, potential barrier is reduced, and an on state where current flows is shown.

The electron injected into the oxide semiconductor at this time flows in the oxide semiconductor as illustrated in FIG. 26A. In FIG. 26B, when a negative potential is applied to the gate (GE1), the number of holes that are minority carriers is substantially zero; thus, the current value becomes a value as close to zero as possible.

As described above, an oxide semiconductor is made to be an intrinsic (i-type) semiconductor or made to be a substantially intrinsic semiconductor by being purified so as not to contain impurities which are not main components of the oxide semiconductor as much as possible. Therefore, interface characteristics between the gate insulating film and the oxide semiconductor become obvious, and it is necessary to consider the interface characteristics and the bulk characteristics separately. Therefore, it is necessary to use a gate insulating film which can form a favorable interface with the oxide semiconductor. For example, it is preferable to use an insulating layer which is formed by a CVD method using high-density plasma generated with a power supply frequency from the VHF band to the microwave band or an insulating film formed by a sputtering method.

When the oxide semiconductor is purified and the interface between the oxide semiconductor and the gate insulating film is favorable, even when the thin film transistor has a channel width W of 1×10⁴ μm and a channel length of 3 μm, an off-state current of 10⁻¹³ A or lower at room temperature and a subthreshold value (S value) of 0.1 V/dec. (the thickness of the gate insulating film: 100 nm) are greatly expected.

As described above, the oxide semiconductor is purified so as to minimize the amount of impurities that are not main components of the oxide semiconductor but contained in the oxide semiconductor, whereby favorable operation of the transistor can be obtained.

In this embodiment, a transistor includes a purified oxide semiconductor layer. The oxide semiconductor layer includes a dense crystalline region including nanocrystals in a surface portion of the oxide semiconductor layer, and the dense crystalline region prevents the transistor from changing into an n-type transistor due to entry of moisture from the superficial portion to the inside of the purified oxide semiconductor layer or elimination of oxygen. Such a transistor having a four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to the purified oxide semiconductor layer, each with an insulating film arranged therebetween is characterized by a positive threshold voltage and an extremely small off-state current.

In the case where the fourth electrode layer is used as a main gate electrode, a channel is formed in a region which is provided between a region in contact with the second electrode layer of the oxide semiconductor layer and a region in contact with the third electrode layer of the oxide semiconductor layer, which is in contact with the second insulating layer, and which overlaps with the fourth electrode layer. Note that a region in which the channel is formed is a crystalline region of the oxide semiconductor as well, and includes the crystal grains in which c-axis is oriented in an almost vertical direction with respect to the surface of the oxide semiconductor layer. For example, in the case where an In—Ga—Zn—O-based oxide semiconductor material is used for the oxide semiconductor layer, nanocrystals are arranged so that c-axis of In₂Ga₂ZnO₇ is in a vertical direction with respect to a substrate plane (or a surface of the oxide semiconductor layer), whereby current flows through the transistor in a b-axis direction (or an a-axis direction) of In₂Ga₂ZnO₇. Therefore, the transistor in which the fourth electrode layer is used as a main gate electrode exhibits high dynamic characteristics (on characteristics or frequency characteristics (referred to as f characteristics)), and thus can favorably be used as a transistor for a driver circuit to which high-speed operation is required.

In the case where the first electrode layer is used as a main gate electrode, a channel is formed in a region which is provided between a region in contact with the second electrode layer of the oxide semiconductor layer and a region in contact with the third electrode layer of the oxide semiconductor layer, which is in contact with the first insulating layer, and where overlaps with the first electrode layer. Note that in the oxide semiconductor layer which becomes i-type or becomes substantially i-type (an oxide semiconductor layer which is purified) due to removal of an impurity, the carrier concentration is suppressed. In addition, a dense crystalline region including nanocrystals exists on the side opposite to a channel formation region of the oxide semiconductor layer, and thus, a change to an n-type, which is attributed to entry of moisture from the superficial portion or elimination of oxygen, can be prevented. Therefore, the transistor in which the first electrode layer is used as a main gate electrode has an extremely small off-state current and excellent reliability, and thus can favorably be used as a transistor for a pixel portion to which a reduction of a leakage current is required.

As described above, by selecting a mainly used gate electrode, electric characteristics of the transistor having a four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer including a crystalline region in a surface portion of the oxide semiconductor layer, each with an insulating film arranged therebetween can be selected.

A plurality of transistors each having a four-terminal structure in which a pair of electrode layers are formed over one substrate in a channel formation region of an oxide semiconductor layer including a crystalline region in a surface portion of the oxide semiconductor layer. The electrode layers are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween. A mainly used gate electrode is selected, and thus, a plurality of transistors having different characteristics and provided over one substrate can be operated.

In addition, a semiconductor device including a driver circuit which is capable of high-speed operation and a pixel portion whose power consumption is suppressed can be manufactured over one substrate.

Note that in the transistor which is one embodiment of the present invention, the mainly used gate electrode is not necessarily fixed to the first electrode layer or the fourth electrode layer. The mainly used gate electrode can be changed as appropriate in accordance with the operation state and the operation load of the circuit. Note that this embodiment can be freely combined with any of the other embodiments.

(Embodiment 2)

In Embodiment 2, an example of forming an inverter circuit of a driver circuit using two transistors each having a four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween is described with reference to FIGS. 3A, 3B, and 3C. Transistors in FIG. 3A are the same as the transistors 440A and 440B in FIG. 1E of Embodiment 1, and thus the same parts are denoted by the same reference numerals.

A driver circuit for driving a pixel portion may be provided in the periphery of the pixel portion, and is formed using an inverter circuit, a capacitor, a resistor, or the like. In one embodiment of the inverter circuit, the inverter circuit is formed using two n-channel transistors in combination. For example, there are an inverter circuit having a combination of an enhancement transistor and a depletion transistor (hereinafter, referred to as an EDMOS circuit) and an inverter circuit having a combination of two enhancement transistors (hereinafter, referred to as an EEMOS circuit).

FIG. 3A illustrates a cross-sectional structure of the inverter circuit of the driver circuit. Since a first transistor 440A and a second transistor 440B can be formed by a method similar to the method described in Embodiment 1, detailed description is omitted. Note that it is preferable to form a contact hole 408 in a second insulating layer 428 and then, form a fourth electrode layer 422 a and a fourth electrode layer 422 b, and directly connect a second wiring 410 b and the fourth electrode layer 422 b each connected to a second electrode layer 455 c through the contact hole 408. The number of contact holes needed for a connection is small, so that not only the electric resistance but also an area occupied by the contact hole can be reduced.

A first wiring 410 a connected to a second electrode layer 455 a in the first transistor 440A is a power supply line to which negative voltage VDL is applied (a negative power supply line). This power supply line may be a power supply line with a ground potential (a ground potential power supply line).

Further, a third wiring 410 c connected to a third electrode layer 455 d in the second transistor 440B is a power supply line to which positive voltage VDH is applied (a positive power supply line).

Further, FIG. 3C is a top view of the inverter circuit of the driver circuit. In FIG. 3C, a cross section taken along the chain line Z1-Z2 corresponds to FIG. 3A.

Further, an equivalent circuit of the EDMOS circuit is illustrated in FIG. 3B. The circuit connection illustrated in FIG. 3B corresponds to that illustrated in FIG. 3A. An example in which the first transistor 440A is an enhancement n-channel transistor and the second transistor 440B is a depletion n-channel transistor is illustrated.

In Embodiment 2, a first electrode and a fourth electrode which are provided on opposite sides from each other with respect to a channel formation region of a purified oxide semiconductor layer, each with an insulating film arranged therebetween are used in order to control the threshold value of the first transistor 440A and the second transistor 440B. Specifically, voltage is applied to each of the first electrode and the fourth electrode so that the first transistor 440A becomes an enhancement transistor and the second transistor 440B becomes a depletion transistor.

Note that although the example in which the second wiring 410 b is directly connected to the fourth electrode layer 422 b through the contact hole 408 formed in the second insulating layer 428 is illustrated in FIGS. 3A and 3C, without particular limitations, a connection electrode may be additionally provided so as to electrically connect the second wiring 410 b and the fourth electrode layer 422 b. Further, although the fourth electrode layer of the second transistor 440B is used as a main gate electrode in this embodiment, the first electrode layer of the second transistor 440B may be used as a main gate electrode. In such a case, it is not necessary that the contact hole 408 is provided in the second insulating layer 428, and a contact hole connects to the second electrode layer 455 c and the first electrode layer 421 b is formed in the first insulating layer 402.

As described above, the inverter circuit can be formed using two transistors with the four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween. The threshold value of the transistors is controlled by using the first electrode layer and the fourth electrode layer of the dual-gate structure, whereby the enhancement transistor and the depletion transistor can be formed over one substrate without forming oxide semiconductor films additionally, and thus the manufacturing process is simple.

In addition, the inverter circuit to which the transistor of one embodiment of the present invention in which the fourth electrode layer is used as a main gate electrode has favorable dynamic characteristics.

In addition, this embodiment can be freely combined with any of the other embodiments.

(Embodiment 3)

In this embodiment, an example of manufacturing a pulse output circuit using a transistor in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween. Further, an example of manufacturing a shift register by connecting a plurality of such pulse output circuits will be described with reference to FIGS. 4A to 4C and FIGS. 5A and 5B.

Note that a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel region between a drain region and a source region, and current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain of the transistor may change depending on the structure, the operating condition, and the like of the transistor, it is difficult to define which is a source or a drain. Therefore, regions functioning as source and drain are not called the source and the drain in some cases. In such a case, for example, one of the source and the drain may be referred to as a first terminal and the other may be referred to as a second terminal.

FIG. 4A illustrates a structure of a shift register. The shift register includes a first to N-th pulse output circuits 10_1 to 10_N (N is a natural number greater than or equal to 3).

The first to N-th pulse output circuits 10_1 to 10_N are connected to a first wiring 11, a second wiring 12, a third wiring 13, and a fourth wiring 14. A first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4 are supplied from the first wiring 11, the second wiring 12, the third wiring 13, and the fourth wiring 14, respectively.

Note that a clock signal (CK) is a signal that alternates between an H level (also referred to as an H signal or a signal at high power supply potential level) and an L level (also referred to as an L signal or a signal at low power supply potential level) at regular intervals. Here, the first to fourth clock signals (CK1) to (CK4) are delayed by ¼ period sequentially. In this embodiment, driving or the like of the pulse output circuits is controlled with the first to fourth clock signals (CK1) to (CK4). Note that the clock signal is also referred to as GCK or SCK in some cases depending on a driver circuit to which the clock signal is input; the clock signal is referred to as CK in the following description.

Each of the first to N-th pulse output circuits 10_1 to 10_N includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 4B). Although not illustrated, each of the first to N-th pulse output circuits 10_1 to 10_N is connected to a power supply line 51, a power supply line 52, and a power supply line 53.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 of each of the pulse output circuits are electrically connected to any of the first to fourth wirings 11 to 14. For example, in the first pulse output circuit 10_1 in FIG. 4A, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. In the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14.

A start pulse SP1 (a first start pulse) is input from a fifth wiring 15 to the first pulse output circuit 10_1. To the n-th pulse output circuit 10_n of the second or subsequent stage (n is a natural number greater than or equal to 2 and less than or equal to N), a signal from the pulse output circuit of the preceding stage (such a signal is referred to as a preceding-stage signal OUT(n−1)) (n is a natural number greater than or equal to 2) is input.

In addition, a signal from the third pulse output circuit 10_3 is input to the first pulse output circuit 10_1 in the two stages before the third pulse output circuit 10_3. In a similar manner, a signal from the (n+2)-th pulse output circuit 10_(n+2) in two stages after the n-th pulse output circuit 10_n (such a signal is referred to as a subsequent-stage signal OUT(n+2)) is input to the n-th pulse output circuit 10_n in the second or subsequent stage. Therefore, from the pulse output circuit in each stage, a first output signal (OUT(1)(SR) to OUT(N)(SR)) to be input to a pulse output circuit in the next stage and/or in two stages before the pulse output circuit and a second output signal (OUT(1) to OUT(N)) for electrical connection to another wiring or the like are output.

That is, in the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21; the second clock signal CK2 is input to the second input terminal 22; the third clock signal CK3 is input to the third input terminal 23; a start pulse is input to the fourth input terminal 24; a subsequent-stage signal OUT(3) is input to the fifth input terminal 25; the first output signal OUT(1)(SR) is output from the first output terminal 26; and the second output signal OUT(1) is output from the second output terminal 27.

As illustrated in FIG. 4A, the subsequent-stage signal OUT(n+2) is not input to the last two stages of the shift register (10_N−1, 10_N). For example, a second start pulse SP2 from a sixth wiring 16 and a third start pulse SP3 from a seventh wiring 17 may be input to the pulse output circuits 10_N−1 and 10_N, respectively. Alternatively, a signal which is additionally generated in the shift register may be input. For example, an (N+1)-th pulse output circuit 10_(N+1) and an (N+2)-th pulse output circuit 10_(N+2) which do not contribute to output of pulses to the pixel portion (such circuits are also referred to as dummy stages) may be provided so that signals corresponding to the second start pulse (SP2) and the third start pulse (SP3) are generated in the dummy stages.

Next, a structure of a pulse output circuit of an embodiment of the present invention will be described with reference to FIG. 4C.

The first to N-th pulse output circuits 10_1 to 10_N are connected to the power supply line 51, the power supply line 52, and the power supply line 53. A first high power supply potential VDD, a second high power supply potential VCC, and a low power supply potential VSS are supplied through the power supply line 51, the power supply line 52, and the power supply line 53, respectively. Here, the relation of the power supply potentials of the power supply lines 51 to 53 is for example as follows: the first high power supply potential VDD is higher than or equal to the second high power supply potential VCC, and the second high power supply potential VCC is higher than the low power supply potential VSS. By making the potential VCC of the power supply line 52 lower than the potential VDD of the power supply line 51, a potential applied to a gate electrode of a transistor can be lowered, shift in threshold voltage of the transistor can be reduced, and deterioration of the transistor can be suppressed without an adverse effect on the operation of the transistor.

Note that the first to fourth clock signals (CK1) to (CK4) each alternate between an H level and an L level at regular intervals; the clock signal at the H level is VDD and the clock signal at the L level is VSS.

The first to N-th pulse output circuits 10_1 to 10_N each include a first to eleventh transistors 31 to 41 (see FIG. 4C). In this embodiment, a pulse output circuit is formed by forming two kinds of transistors over one substrate. Since the first to N-th pulse output circuits 10_1 to 10_N included in the shift register exemplified in this embodiment have the same configuration, the structure and operation of the first pulse output circuit 10_1 are described here.

The first pulse output circuit 10_1 includes a first to eleventh transistors 31 to 41. The first to eleventh transistors 31 to 41 are n-channel transistors each including a purified oxide semiconductor layer.

Note that in a purified oxide semiconductor layer of one embodiment of the present invention, a dense crystalline region including nanocrystals exists in a surface portion of the oxide semiconductor layer and prevents the transistor from changing into an n-type transistor due to entry of moisture from the superficial portion or elimination of oxygen. Such a transistor having the four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a purified oxide semiconductor layer, each with an insulating film arranged therebetween is characterized by a positive threshold voltage and an extremely small off-state current.

A transistor in which a first electrode layer arranged on the substrate side with a first insulating layer provided therebetween is used as a main gate electrode and where the surface portion of the oxide semiconductor layer in which the crystalline region is formed is on the back channel side has an extremely small off-state current and excellent reliability. Therefore, in this embodiment, the transistor in which the first electrode layer is applied to a main gate electrode is used as a second transistor 32 and a fifth transistor 35.

Note that the transistor in which the first electrode layer is used as a main gate electrode is also suitable for transistors, to a gate electrode of which signals are directly input from the outside, in a pulse output circuit and a shift register formed by connecting a plurality of such pulse output circuits. For example, in the case of the first pulse output circuit 10_1, the transistor in which the first electrode layer is used as a main gate electrode can be suitably applied to the first transistor 31 and the fifth transistor 35 which are connected to the fourth input terminal 24, to which a start pulse is input from the outside. The transistor in which the first electrode layer is used as a main gate electrode has a high withstand voltage between the gate and the source and between the gate and the drain; therefore, problems such as the shift in threshold value of the transistor included in the circuit caused by abnormal input such as static electricity can be reduced.

A transistor in which a fourth electrode layer arranged on the opposite side to the substrate with a second insulating layer provided therebetween is used as a main gate electrode and in which a channel formation region is included in the surface portion of the oxide semiconductor layer where the crystalline region is formed has high dynamic characteristics. Therefore, in this embodiment, the transistor in which the fourth electrode layer is used as a main gate electrode is applied to a third transistor 33, a sixth transistor 36, a tenth transistor 40, and an eleventh transistor 41.

Note that each of the transistors in which the fourth electrode layer is used as a main gate electrode and the transistor in which the first electrode layer is used as a main gate electrode can be manufactured in accordance with the method described in Embodiment 1. Therefore, detailed description is omitted in this embodiment.

As the first transistor 31, the fourth transistor 34, the seventh transistor 37 to the ninth transistor 39, either the transistor in which the first electrode layer is used as a main gate electrode or the transistor in which the fourth electrode layer is used as a main gate electrode may be used. In this embodiment, the transistor in which the first electrode layer is used as a main gate electrode is applied.

In FIG. 4C, a first terminal of the first transistor 31 is electrically connected to the power supply line 51, a second terminal of the first transistor 31 is electrically connected to a first terminal of the ninth transistor 39, and a gate electrode of the first transistor 31 is electrically connected to the fourth input terminal 24. A first terminal of the second transistor 32 is electrically connected to the power supply line 53, a second terminal of the second transistor 32 is electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the second transistor 32 is electrically connected to a gate electrode of the fourth transistor 34. A first terminal of the third transistor 33 is electrically connected to the first input terminal 21, and a second terminal of the third transistor 33 is electrically connected to the first output terminal 26. A first terminal of the fourth transistor 34 is electrically connected to the power supply line 53, and a second terminal of the fourth transistor 34 is electrically connected to the first output terminal 26. A first terminal of the fifth transistor 35 is electrically connected to the power supply line 53, and a second terminal of the fifth transistor 35 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode of the fifth transistor 35 is electrically connected to the fourth input terminal 24. A first terminal of the sixth transistor 36 is electrically connected to the power supply line 52, a second terminal of the sixth transistor 36 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode of the sixth transistor 36 is electrically connected to the fifth input terminal 25. A first terminal of the seventh transistor 37 is electrically connected to the power supply line 52, a second terminal of the seventh transistor 37 is electrically connected to a second terminal of the eighth transistor 38, and a gate electrode of the seventh transistor 37 is electrically connected to the third input terminal 23. A first terminal of the eighth transistor 38 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and a gate electrode of the eighth transistor 38 is electrically connected to the second input terminal 22. The first terminal of the ninth transistor 39 is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, a second terminal of the ninth transistor 39 is electrically connected to a gate electrode of the third transistor 33 and a gate electrode of the tenth transistor 40, and a gate electrode of the ninth transistor 39 is electrically connected to the power supply line 52. A first terminal of the tenth transistor 40 is electrically connected to the first input terminal 21, a second terminal of the tenth transistor 40 is electrically connected to the second output terminal 27, and the gate electrode of the tenth transistor 40 is electrically connected to the second terminal of the ninth transistor 39. A first terminal of the eleventh transistor 41 is electrically connected to the power supply line 53, a second terminal of the eleventh transistor 41 is electrically connected to the second output terminal 27, and a gate electrode of the eleventh transistor 41 is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34.

In FIG. 4C, the point at which the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 are connected is referred to as a node A. Further, the point at which the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 are connected is referred to as a node B. A capacitor having one electrode electrically connected to the node B may be additionally provided in order to hold a potential of the node B. Specifically, a capacitor having one electrode electrically connected to the node B and the other electrode electrically connected to the power supply line 53 may be provided.

Next, operation of a pulse output circuit illustrated in FIG. 5A will be described with reference to FIG. 5B, FIGS. 6A to 6D, FIGS. 7A to 7D, and FIGS. 8A and 8B. Specifically, operation of the pulse output circuit will be described in separate periods: a first period 61, a second period 62, a third period 63, a fourth period 64, and a fifth period 65 in a timing chart of FIG. 5B. In FIGS. 6A to 6D and FIGS. 7A to 7D, transistors indicated by a solid line is in an ON state (a conductive state) and transistors indicated by a broken line is in an OFF state (a non-conductive state).

Here, the output of the first pulse output circuit 10_1 is described. The first input terminal 21 of the first pulse output circuit 10_1 is electrically connected to the first wiring 11 through which the first clock signal (CK1) is supplied, the second input terminal 22 is electrically connected to the second wiring 12 through which the second clock signal (CK2) is supplied, and the third input terminal 23 is electrically connected to the third wiring 13 through which the third clock signal (CK3) is supplied.

In the following description, the first to eleventh transistors 31 to 41 are n-channel transistors and are turned on when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

Further, for simplicity, description is made under the assumption that VSS is 0 here; however, the present invention is not limited thereto. A difference between VDD and VCC and a difference between VCC and VSS (in the case where the following relation is satisfied: VDD>VCC) are each higher than the threshold voltages of the transistors, that is, such differences can make the transistors in an ON state (a conductive state). When the potential of the power supply line 52 is lower than the potential of the power supply line 51, a potential applied to the gate electrodes of the second transistor 32, the fourth transistor 34, the ninth transistor 39, and the eleventh transistor 41 can be suppressed to be low; the shift of the threshold value of the second transistor 32, the fourth transistor 34, the ninth transistor 39, and the eleventh transistor 41 in the pulse output circuit can be reduced; and deterioration can be suppressed.

In the first period 61, the first start pulse (SP1) changes into an H level, so that the first transistor 31 and the fifth transistor 35, which are electrically connected to the fourth input terminal 24 of the first pulse output circuit 10_1 to which the first start pulse (SP1) is input, change into a conductive state. Since the third clock signal (CK3) is also at an H level, the seventh transistor 37 is also turned on. In addition, the second high power supply potential VCC is applied to the gate of the ninth transistor 39, thereby turning on the ninth transistor 39 (see FIG. 6A).

At this time, since the first transistor 31 and the ninth transistor 39 are on, the potential of the node A is increased. Meanwhile, since the fifth transistor 35 is on, the potential of the node B decreases.

The second terminal of the first transistor 31 serves as a source, and the potential of the second terminal of the first transistor 31 has such a value that is obtained by subtracting the threshold voltage of the first transistor 31 from the potential of the first power supply line 51, which can be expressed by VDD−Vth31 (Vth31 is a threshold voltage of the first transistor 31). When (VDD−Vth31) is higher than or equal to (VCC−Vth39) where Vth39 is a threshold voltage of the ninth transistor 39, the potential of the node A is (VCC−Vth39), whereby the ninth transistor 39 is turned off. The node A is in a floating state, maintaining the potential (VCC−Vth39). When (VDD−Vth31) is lower than (VCC−Vth39), the ninth transistor 39 is not turned off and the potential of the node A is increased to (VDD−Vth31).

In this embodiment, since the first transistor 31 to the eleventh transistor 41 all have the same threshold voltage Vth0, the potential of the node A is (VCC−Vth0) and the ninth transistor 39 is turned off. The node A is in a floating state, maintaining the potential (VCC−Vth0).

Here, the potential of the gate electrode of the third transistor 33 is (VCC−Vth0). The gate-source voltage of the third transistor 33 is higher than the threshold voltage thereof, that is, the following relation is obtained: VCC−Vth0>Vth33 (Vth33 is a threshold voltage of the third transistor 33 and is, in this embodiment, Vth0). Accordingly, the third transistor 33 is turned on.

In the second period 62, the first clock signal (CK1) supplied to the first input terminal 21 of the first pulse output circuit 10_1 is changed from an L level to an H level. Since the third transistor 33 has already been on, current flows between the source and the drain, and the potential of the output signal (OUT(1)(SR)) output from the output terminal 26, that is, the potential of the second electrode (the source electrode in this case) of the third transistor 33 starts increasing. There exists capacitive coupling due to parasitic capacitance between the gate and the source and the channel capacitance of the third transistor 33, and with the increase in the potential of the output terminal 26, the potential of the gate electrode of the third transistor 33 which is in a floating state is increased (bootstrap operation). Finally, the potential of the gate electrode of the third transistor 33 becomes higher than (VDD+Vth33) and the potential of the output terminal 26 becomes equal to VDD (see FIG. 5B and FIG. 6B).

At this time, since the fourth input terminal 24 of the first pulse output circuit 10_1 has an H level due to the supply of the first start pulse (SP1), the fifth transistor 35 is on, and the L level is maintained at the node B. Accordingly, when the potential of the output terminal 26 rises from an L level to an H level, a malfunction due to capacitive coupling between the output terminal 26 and the node B can be suppressed.

Next, in the first half of the third period 63, the first start pulse (SP1) changes into an L level, so that the first transistor 31 and the fifth transistor 35 are turned off. The first clock signal (CK1) keeps the H level from the second period 62, and the potential of the node A does not change as well; therefore, an H level signal is supplied to the first electrode of the third transistor 33 (see FIG. 6C). In the first half of the third period 63, each transistor connected to the node B is turned off, so that the node B is in a floating state. However, the potential of the output terminal 26 does not change, so that the influence from a malfunction due to capacitive coupling between the node B and the output terminal 26 is negligible.

Note that by providing the ninth transistor 39 having the gate to which the second high power supply potential VCC is applied as illustrated in FIG. 5A, the following advantages before and after the bootstrap operation are obtained.

Without the ninth transistor 39 having the gate electrode to which the second high power supply potential VCC is applied, if the potential of the node A is raised by the bootstrap operation, the potential of the source which is the second terminal of the first transistor 31 rises to a value higher than the first high power supply potential VDD. Then, the first terminal of the first transistor 31, that is, the terminal on the power supply line 51 side, comes to serve as a source of the first transistor 31. Consequently, in the first transistor 31, a high bias voltage is applied and thus significant stress is applied between the gate and the source and between the gate and the drain, which might cause deterioration of the transistor.

On the other hand, with the ninth transistor 39 having the gate electrode to which the second high power supply potential VCC is applied, increase in the potential of the second terminal of the first transistor 31 can be prevented even when the potential of the node A is raised by the bootstrap operation. In other words, provision of the ninth transistor 39 can lower the level of negative bias voltage applied between the gate and the source of the first transistor 31. Thus, the circuit configuration in this embodiment can reduce negative bias voltage applied between the gate and the source of the first transistor 31, so that deterioration of the first transistor 31 due to stress can be reduced.

Note that the ninth transistor 39 can be provided anywhere as long as the first terminal and the second terminal of the ninth transistor 39 are connected between the second terminal of the first transistor 31 and the gate of the third transistor 33. Note that when the shift register including a plurality of pulse output circuits in this embodiment is included in a signal line driver circuit for which higher dynamic characteristics are required than a scan line driver circuit, the ninth transistor 39 may be omitted, which is advantageous in that the number of transistors is reduced.

In the latter half of the third period 63, the third clock signal (CK3) is changed into an H level, whereby the seventh transistor 37 is turned on. The second clock signal (CK2) keeps the H level from the first half of the third period 63, and the eighth transistor 38 is on, so that the potential of the node B is increased to VCC.

Since the potential of the node B is increased, the second transistor 32, the fourth transistor 34, and the eleventh transistor 41 change into an ON state, so that the potential of the output terminal 27 (OUT(1)) becomes an L level.

In the latter half of the third period 63, the second transistor 32 is turned on and an L level signal is supplied to the first terminal of the ninth transistor 39; thus, the ninth transistor 39 changes into an ON state and the potential of the node A is decreased.

Since the fourth transistor 34 changes into an ON state, the potential of the output terminal 26 is decreased (see FIG. 6D).

In the first half of the fourth period 64, the second clock signal (CK2) is changed from an H level to an L level, whereby the eighth transistor 38 is turned off However, because the fifth input terminal 25 (OUT(3)) keeps the H level to keep the sixth transistor 36 in an ON state, the node B maintains VCC (see FIG. 7A).

In the latter half of the fourth period 64, the fifth input terminal 25 (OUT(3)) of the first pulse output circuit 10_1 changes into an L level, whereby the sixth transistor 36 is turned off (see FIG. 7B). At this time, the node B changes from a state of holding a VCC level into a floating state. Accordingly, the second transistor 32, the fourth transistor 34, and the eleventh transistor 41 keep an ON state. Note that as illustrated in FIG. 5B, the potential of the node B is decreased from the VCC level due to an off-state current of a transistor or the like.

Then, the circuit cyclically repeats the operation. Such a period is referred to as a fifth period 65 (see FIG. 7C and FIG. 7D). In a certain period in the fifth period 65 (a period when the second clock signal (CK2) and the third clock signal (CK3) are both at an H level), the seventh transistor 37 and the eighth transistor 38 are turned on and a signal at a VCC level is regularly supplied to the node B (see FIG. 7D).

With the structure in which a signal at a VCC level is regularly supplied to the node B in the fifth period 65, a malfunction of the pulse output circuit can be suppressed. In addition, by regularly turning on or off the seventh transistor 37 and the eighth transistor 38, a shift of a threshold value of the transistor can be reduced.

In the fifth period 65, in the case where the potential of the node B is decreased during the time when the signal at a VCC level is not supplied from the second power supply line 52 to the node B, the node B may be provided with a capacitor in advance to reduce the decrease in the potential of the node B.

Although the second input terminal 22 is connected to the gate electrode of the eighth transistor 38 and the third input terminal 23 is connected to the seventh transistor 37 in the drawing, the connection relation may be changed so that the clock signal that has been supplied to the gate electrode of the eighth transistor 38 is supplied to the gate electrode of the seventh transistor 37 and the clock signal that has been supplied to the gate electrode of the seventh transistor 37 is supplied to the gate electrode of the eighth transistor 38. Even with this structure, a similar effect can be obtained.

In the pulse output circuit illustrated in FIG. 5A, if potentials of the second input terminal 22 and the third input terminal 23 are controlled so that the state is changed from the state where the seventh transistor 37 and the eighth transistor 38 are both on, to the state where the seventh transistor 37 is off and the eighth transistor 38 is still on, and then to the state where the seventh transistor 37 and the eighth transistor 38 are both off, a fall in the potential of the node B occurs twice because of the fall in the potential of the gate electrode of the seventh transistor 37 and the fall in the potential of the gate electrode of the eighth transistor 38.

On the other hand, in the pulse output circuit illustrated in FIG. 5A, when the state is changed from the state where the seventh transistor 37 and the eighth transistor 38 are both on, to the state where the seventh transistor 37 is still on and the eighth transistor 38 is off, and then to the state where the seventh transistor 37 and the eighth transistor 38 are both off as illustrated in FIG. 5B, the fall in the potential of the node B occurs only once because of the fall in the potential of the gate electrode of the eighth transistor 38. Thus, the number of falls in the potential can be reduced to one.

In other words, it is preferable that the clock signal is supplied from the third input terminal 23 to the gate electrode of the seventh transistor 37 and the clock signal is supplied from the second input terminal 22 to the gate electrode of the eighth transistor 38 because the fluctuation in the potential of the node B can be reduced and therefore noise can be reduced.

In such a manner, a signal at a VCC level is regularly supplied to the node B in a period during which the potentials of the first output terminal 26 and the second output terminal 27 are held at an L level; thus, a malfunction of the pulse output circuit can be suppressed.

In the latter half of the fourth period 64, the node B in the pulse output circuit described in this embodiment changes from a state of holding a VCC level into a floating state. There is a fear that the potential of the node B in the floating state may be decreased from the VCC level due to an off-state current or the like of the fifth transistor 35. However, the fifth transistor 35 of the pulse output circuit of this embodiment is a transistor having an extremely small off-state current, in which the first electrode layer is used as a main gate electrode. Therefore, the potential of the node B in the floating state is maintained stably and a reduction from the VCC level is small. Accordingly, a malfunction of the semiconductor device is suppressed and reliability is increased.

In addition, there is no need to employ a multi-gate structure such as a double-gate structure or a triple-gate structure for suppression of an off-state current of a transistor; therefore, the transistor can be miniaturized. Further, a capacitor for maintaining the potential of the node B is unnecessary or can be miniaturized. In this manner, the total size of the semiconductor device can be reduced by using a pulse output circuit including a miniaturized element or a shift register including a miniaturized pulse output circuit.

The transistor in which the first electrode layer is used as a main gate electrode has not only an off-state current that is reduced to be extremely small but also a positive threshold voltage. In the pulse output circuit of this embodiment, the transistor in which the first electrode layer is used as a main gate electrode is employed as the second transistor 32. Thus, the potential of the node A can be increased speedily by the bootstrap operation without much loss. Therefore, a malfunction of the semiconductor device is suppressed and reliability is increased.

In the pulse output circuit of this embodiment, transistors in each of which the fourth electrode layer using a crystalline region of a purified oxide semiconductor layer is used as a main gate electrode are used as the third transistor 33, the sixth transistor 36, the tenth transistor 40, and the eleventh transistor 41. The transistor in which the fourth electrode layer is used as a main gate electrode has excellent f characteristics and a high field-effect mobility. Therefore, switching operation of the third transistor 33, the sixth transistor 36, the tenth transistor 40, and the eleventh transistor 41 can be made faster. In addition, the transistors can be miniaturized.

Thus, the semiconductor device can operate at high speed by using a pulse output circuit including an element which operates at high speed or a shift register including a pulse output circuit which operates at high speed.

In addition, the shift register described in this embodiment uses a driving method in which a pulse that is output from the m-th pulse output circuit overlaps with half (¼ period) of a pulse that is output from the (m+1)-th pulse output circuit, as shown in FIG. 8A. This can make the time of charging a wiring with electricity twice as long as that in a driving method in which a pulse that is output from the m-th pulse output circuit does not overlap with a pulse that is output from the (m+1)-th pulse output circuit in a conventional shift register (see FIG. 8B). In this way, by using a driving method in which a pulse that is output from the m-th pulse output circuit overlaps with half (¼ period) of a pulse that is output from the (m+1)-th pulse output circuit, a pulse output circuit which can withstand large load and operate at a high frequency can be provided. In addition, an operating condition of a pulse output circuit can be improved.

Note that the shift register and the pulse output circuit described in this embodiment can be combined with any structure of a shift register and a pulse output circuit described in the other embodiments of this specification. This embodiment of the present invention can also be applied to a semiconductor device. A semiconductor device in this specification means a device that can function by utilizing semiconductor characteristics.

(Embodiment 4)

In this embodiment, an example of forming a driver circuit of an active matrix display device by combining the shift register described in Embodiment 3 manufactured using transistors having the four-terminal structure in which a pair of electrode layers which are provided on opposite sides from each other with respect to a channel formation region of an oxide semiconductor layer, each with an insulating film arranged therebetween, with a switching circuit using a transistor in which a purified oxide semiconductor layer is used will be described. First, an overview of the active matrix display device is described with reference to block diagrams, and then a signal line driver circuit and a scan line driver circuit utilizing the shift register, which are provided for the display device, are described.

FIG. 9A illustrates an example of a block diagram of an active matrix display device. A pixel portion 5301, a first scan line driver circuit 5302, a second scan line driver circuit 5303, and a signal line driver circuit 5304 are provided over a substrate 5300 in the display device. In the pixel portion 5301, a plurality of signal lines extended from the signal line driver circuit 5304 is arranged and a plurality of scan lines extended from the first scan line driver circuit 5302 and the second scan line driver circuit 5303 is arranged. Note that in cross regions of the scan lines and the signal lines, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) through a connection portion such as a flexible printed circuit (FPC).

As a transistor disposed in the pixel portion 5301, a transistor of an embodiment described in Embodiment 1 can be employed. A transistor in which a first electrode layer provided in a side where a substrate is formed with a first insulating layer located therebetween is used as a main gate electrode is preferably used in the pixel portion 5301. Since a transistor in which the first electrode layer is used as a main electrode has a small off-state current, contrast of a display image can be increased and further power consumption of the display device can be reduced.

Since the transistors described in Embodiments 1 are n-channel transistors, some of driver circuits that can be constituted by n-channel transistors among the driver circuits are formed over the substrate where the transistor of the pixel portion is formed.

In FIG. 9A, the first scan line driver circuit 5302, the second scan line driver circuit 5303, and the signal line driver circuit 5304 are formed over the substrate 5300 where the pixel portion 5301 is formed. Consequently, the number of components of a driver circuit and the like that are provided outside the display device is reduced, so that cost can be reduced. Further, if the driver circuit is provided outside the substrate 5300, wirings need to be extended and the number of connections of wirings is increased. However, by providing the driver circuit over the substrate 5300, the number of connections of the wirings can be reduced. Accordingly, an improvement in reliability or an increase in yield can be achieved.

Note that the timing control circuit 5305 supplies, for example, a first scan line driver circuit start signal (GSP1) and a scan line driver circuit clock signal (GCK1) to the first scan line driver circuit 5302. Furthermore, the timing control circuit 5305 supplies, for example, a second scan line driver circuit start signal (GSP2) (which is also referred to as a start pulse) and a scan line driver circuit clock signal (GCK2) to the second scan line driver circuit 5303. Moreover, the timing control circuit 5305 supplies a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal (SCK), video signal data (DATA, also simply referred to as a video signal), and a latch signal (LAT) to the signal line driver circuit 5304. Each clock signal may be a plurality of clock signals with shifted phases or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scan line driver circuit 5302 and the second scan line driver circuit 5303.

FIG. 9B illustrates a structure in which circuits with relatively low driving frequency (e.g., the first scan line driver circuit 5302 and the second scan line driver circuit 5303) are formed over the substrate 5300 where the pixel portion 5301 is formed, and the signal line driver circuit 5304 with relatively high driving frequency is formed over a substrate which is different from the substrate 5300 where the pixel portion 5301 is formed. For example, the signal line driver circuit 5304 with relatively high driving frequency can be formed over a different substrate with the use of a transistor in which a single crystal semiconductor is used. Thus, increase in size of the display device, reduction in the number of steps, reduction in cost, improvement in yield, or the like can be achieved.

In this embodiment, the signal line driver circuit 5304 with relatively high driving frequency is formed over the same substrate 5300 as the pixel portion 5301. By providing the driver circuit over the substrate 5300, the number of connections of wirings can be reduced. Accordingly, an improvement in reliability or an increase in yield can be achieved.

Next, an example of a structure and operation of a signal line driver circuit constituted by n-channel transistors will be described with reference to FIGS. 10A and 10B.

The signal line driver circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors 5603_1 to 5603_k (k is a natural number). In this embodiment, a structure in which the transistors 5603_1 to 5603_k are n-channel transistors is described below.

A connection relation in the signal line driver circuit is described using the switching circuit 5602_1 as an example with reference to FIG. 10A. First terminals of the transistors 5603_1 to 5603_k are connected to wirings 5604_1 to 5604_k, respectively. Second terminals of the transistors 5603_1 to 5603_k are connected to signal lines S1 to Sk, respectively. Gates of the transistors 5603_1 to 5603_k are connected to a wiring 5605_1.

The shift register 5601 has a function of sequentially selecting the switching circuits 5602_1 to 5602_N by sequentially outputting H-level signals (also referred to as H signals or signals at high power supply potential levels) to wirings 5605_1 to 5605_N. The shift register 5601 can be manufactured using the method described in Embodiment 3 and detailed description thereof is omitted here.

The switching circuit 5602_1 has a function of controlling electrical continuity between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk (electrical continuity between the first terminals and the second terminals), that is, a function of controlling whether potentials of the wirings 5604_1 to 5604_k are supplied to the signal lines S1 to Sk. In this manner, the switching circuit 5602_1 functions as a selector. Moreover, the transistors 5603_1 to 5603_k have functions of controlling electrical continuity between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, respectively, that is, functions of supplying potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk, respectively. In this manner, each of the transistors 5603_1 to 5603_k functions as a switch.

In this embodiment, transistors in which a crystalline region of a purified oxide semiconductor layer is used for a channel formation region are used as transistors in the switching circuit 5602. The transistor in which a fourth electrode layer is used as a main gate electrode has excellent dynamic characteristics and fast switching operation. Accordingly, the transistor can be used for high-speed writing which is required in a next-generation high-definition display device including many pixels. Note that since the transistor in which a purified oxide semiconductor layer is used for a channel formation region can be manufactured using the method described in Embodiment 1, detailed description thereof is omitted here.

The video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an analog signal that corresponds to an image signal or image data.

Next, the operation of the signal line driver circuit in FIG. 10A is described with reference to a timing chart in FIG. 10B. FIG. 10B illustrates examples of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are examples of output signals from the shift register 5601. The signals Vdata_1 to Vdata_k are examples of signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driver circuit corresponds to one gate selection period in a display device. For example, one gate selection period is divided into periods T1 to TN. Each of the periods T1 to TN is a period for writing the video signal data (DATA) into a pixel in a selected row.

Note that signal waveform distortion and the like in each structure illustrated in drawings and the like in this embodiment are exaggerated for simplicity in some cases. Therefore, this embodiment is not necessarily limited to the scale illustrated in the drawings and the like.

In the periods T1 to TN, the shift register 5601 sequentially outputs H-level signals to the wirings 5605_1 to 5605_N. For example, in the period T1, the shift register 5601 outputs an H-level signal to the wiring 5605_1. Then, the transistors 5603_1 to 5603_k are turned on, so that the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into conduction. At this time, Data(S1) to Data(Sk) are input to the wirings 5604_1 to 5604_k, respectively. The Data(S1) to Data(Sk) are written into pixels in a first to kth columns in the selected row through the transistors 5603_1 to 5603_k, respectively. In such a manner, in the periods T1 to TN, the video signal data (DATA) are sequentially written into the pixels in the selected row by k columns.

The video signal data (DATA) are written into pixels by a plurality of columns as described above, whereby the number of video signal data (DATA) or the number of wirings can be reduced. Consequently, the number of connections with an external circuit can be reduced. Moreover, the time for writing can be extended when a video signal is written into pixels by a plurality of columns; thus, insufficient writing of a video signal can be prevented.

The shift register described in Embodiment 3 is employed as the shift register 5601 of the driver circuit in this embodiment; therefore, a malfunction is suppressed and the shift register has high reliability. By using a miniaturized shift register, the total size of the driver circuit can be reduced.

In addition, since transistors in which a crystalline region of a purified oxide semiconductor layer is used for a channel formation region are used in the switching circuit 5602 of the driver circuit in this embodiment, switching operation is fast. Accordingly, the driver circuit exemplified in this embodiment can perform high speed writing to pixels and is favorably used in a next-generation high-definition display device including many pixels.

The shift register described in Embodiment 3 can be applied to a scan line driver circuit as well. The scan line driver circuit includes a shift register. Additionally, the scan line driver circuit may include a level shifter, a buffer, or the like in some cases. In the scan line driver circuit, a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, so that a selection signal is generated. The selection signal generated is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Since the transistors in the pixels of one line have to be turned on at the same time, a buffer that can supply large current is used.

The active matrix display device described in this embodiment is connected to an external device through a terminal portion. A protective circuit is provided in the driver circuit in order to prevent generation of problems such as the shift in threshold value of the transistor which is caused by abnormal input (e.g., static electricity) from the outside. Since the transistor in which the first electrode layer is used as a main electrode have a high withstand voltage between the gate and the source and between the gate and the drain, they can be favorably used as transistors used in the protective circuit.

(Embodiment 5)

In this embodiment, an example of a structure of a terminal portion provided over the same substrate as the transistors will be described with reference to FIGS. 22A1 to 22B2. Note that in FIGS. 22A1 to 22B2, components common to those of FIGS. 1A to 1E maintain the same reference numerals.

FIGS. 22A1 and 22A2 respectively illustrate a cross-sectional view and a top view of the terminal portion of the gate wiring. FIG. 22A1 is the cross-sectional view taken along line C1-C2 of FIG. 22A2. In FIG. 22A1, a conductive layer 415 formed over the second insulating layer 428 is a terminal electrode for connection which functions as an input terminal. Furthermore, in a terminal portion of FIG. 22A1, a first terminal 411 formed using the same material as the gate wiring and a connection electrode 412 formed using the same material as the source wiring overlap each other with the first insulating layer 402 interposed therebetween, and are in direct contact with each other so as to be electrically connected to each other. In addition, the connection electrode 412 and the conductive layer 415 are directly connected to each other through a contact hole formed in the second insulating layer 428 so as to be electrically connected to each other.

FIGS. 22B1 and 22B2 respectively illustrate a cross-sectional view and a top view of a source wiring terminal portion. FIG. 22B1 is the cross-sectional view taken along line C3-C4 of FIG. 22B2. In FIG. 22B1, a conductive layer 418 formed over the second insulating layer 428 is a terminal electrode for connection which functions as an input terminal. Further in a terminal portion of FIG. 22B1, an electrode layer 416 formed using the same material as the gate wiring is located below the second terminal 414 so as to overlapped with a second terminal 414 electrically connected to the source wiring with the first insulating layer 402 interposed therebetween. The electrode layer 416 is not electrically connected to the second terminal 414, and a capacitor for preventing noise or static electricity can be formed if the potential of the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, or 0 V. The second terminal 414 is electrically connected to the conductive layer 418, and the second insulating layer 428 is provided therebetween.

A plurality of gate wirings, source wirings, common potential lines, and power supply lines is provided depending on the pixel density. In the terminal portion, a plurality of first terminals at the same potential as the gate wiring, a plurality of second terminals at the same potential as the source wiring, a plurality of third terminals at the same potential as the power supply line, a plurality of fourth terminals at the same potential as the common potential line, and the like are arranged. There is no particular limitation on the number of each of the terminals, and the number of such terminals may be determined by a practitioner as appropriate.

This embodiment can be freely combined with any of the other embodiments.

(Embodiment 6)

By manufacturing transistors described in Embodiment 1 and using the transistors for a pixel portion and driver circuits, a semiconductor device having a display function (also referred to as a display device) can be manufactured. Moreover, some or all of the driver circuits which include the transistors described in Embodiment 1 can be formed over a substrate where the pixel portion is formed, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by a current or a voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. Furthermore, the display device may include a display medium whose contrast is changed by an electric effect, such as electronic ink.

In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel. Furthermore, an element substrate, which is one embodiment before the display element is completed in a manufacturing process of the display device, is provided with a means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state in which only a pixel electrode of the display element is formed, a state in which a conductive film to be a pixel electrode is formed but is not etched yet to form the pixel electrode, or any of the other states.

Note that a display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, the display device also includes any of the following modules in its category: a module to which a connector such as a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP) is attached; a module having a TAB tape or a TCP at the end of which a printed wiring board is provided; and a module having an integrated circuit (IC) that is directly mounted on a display element by a chip on glass (COG) method.

In this embodiment, the appearance and a cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIGS. 11A1, 11A2, and 11B. FIGS. 11A1 and 11A2 are plan views of panels, in which highly reliable transistors 4010 and 4011 each including an In—Ga—Zn—O-based film as an oxide semiconductor layer described in Embodiment 1 and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 11B is a cross-sectional view taken along M-N in FIGS. 11A1 and 11A2.

The sealant 4005 is provided so as to surround a pixel portion 4002 and a scan line driver circuit 4004 which are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Consequently, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on the connection method of the driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 11A1 illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method. FIG. 11A2 illustrates an example in which the signal line driver circuit 4003 is mounted by a TAB method.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of transistors. FIG. 11B illustrates the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scan line driver circuit 4004, as an example. Insulating layers 4020 and 4041 are provided over the transistor 4010, and an insulating layer 4021 is provided over the transistor 4011. The insulating layer 4020 functions as a gate insulating layer of the transistor 4011.

As the transistors 4010 and 4011, highly reliable transistors described in Embodiment 1, each of which includes an In—Ga—Zn—O-based film as an oxide semiconductor layer, can be employed. In this embodiment, the transistors 4010 and 4011 are n-channel transistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with one another corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 functioning as alignment films, respectively, and the liquid crystal layer 4008 is provided between the electrode layers with the insulating layers 4032 and 4033 arranged therebetween. Although not illustrated, a color filter may be provided either on the first substrate 4001 side or on the second substrate 4006 side.

Note that the first substrate 4001 and the second substrate 4006 can be formed of glass, metal (typically, stainless steel), ceramics, or plastics. As plastics, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. Alternatively, a sheet having a structure in which an aluminum foil is arranged between PVF films or polyester films can be used.

A spacer 4035 is a columnar spacer obtained by selective etching of an insulating film and provided in order to control the distance (a cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Alternatively, a spherical spacer may be used. The counter electrode layer 4031 is electrically connected to a common potential line formed over the substrate where the transistor 4010 is formed. The counter electrode layer 4031 and the common potential line can be electrically connected to each other through conductive particles provided between the pair of substrates using the common connection portion. Note that the conductive particles are included in the sealant 4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow range of temperature, a liquid crystal composition containing a chiral agent at 5 wt % or more is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition including liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 10 μsec to 100 μsec inclusive and is optically isotropic; therefore, alignment treatment is not necessary and viewing angle dependence is small.

Note that although a transmissive liquid crystal display device is described as an example in this embodiment, the present invention can also be applied to either a reflective liquid crystal display device or a transflective liquid crystal display device.

Although a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are sequentially provided on the inner surface of the substrate in the liquid crystal display device of this embodiment, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to that in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of the manufacturing process. Further, a light-blocking film functioning as a black matrix may be provided.

In this embodiment, in order to reduce the surface roughness due to the transistor and to improve the reliability of the transistor, the transistors obtained in Embodiment 1 are covered with insulating layers (the insulating layers 4020 and 4021) functioning as a protective film or a planarization insulating film. Note that the protective film is provided to prevent entry of contaminant impurities such as an organic substance, metal, and moisture existing in the air and is preferably a dense film. The protective film may be formed by a sputtering method to have a single-layer structure or a stacked structure including any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and an aluminum nitride oxide film. Although an example in which the protective film is formed by a sputtering method is described in this embodiment, a variety of methods may be employed without limitation to the sputtering method.

In this embodiment, the insulating layer 4020 having a stacked structure is formed as a protective film. Here, a silicon oxide film is formed using a sputtering method as a first layer of the insulating layer 4020. The use of the silicon oxide film as the protective film has an effect of preventing a hillock of an aluminum film which is used as the source and drain electrode layers.

As a second layer of the protective film, an insulating layer is formed. Here, a silicon nitride film is formed using a sputtering method, as the second layer of the insulating layer 4020. The use of the silicon nitride film as the protective film can prevent mobile ions of sodium or the like from entering a semiconductor region, so that variation in electric characteristics of the transistor can be suppressed.

After the protective film is formed, annealing (at higher than or equal to 300° C. and lower than or equal to 400° C.) of the oxide semiconductor layers may be performed.

The insulating layer 4021 is formed as a planarization insulating film. The insulating layer 4021 can be formed using a heat-resistant organic material such as an acrylic resin, polyimide, a benzocyclobutene-based resin, polyamide, or an epoxy resin. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed using any of these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include as a substituent an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. In addition, the organic group may include a fluoro group.

The formation method of the insulating layer 4021 is not limited to a particular method, and the following method can be used depending on the material: a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (such as an inkjet method, screen printing, offset printing, or the like), or the like. Further, the planarization insulating layer 4021 can be formed with a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. In the case of forming the insulating layer 4021 with the use of a liquid material, annealing (at higher than or equal to 300° C. and lower than or equal to 400° C.) of the oxide semiconductor layers may be performed at the same time as a baking step. When the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layers are combined, a semiconductor device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

Alternatively, a conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10000 ohms per square or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. Examples are polyaniline and a derivative thereof, polypyrrole and a derivative thereof, polythiophene and a derivative thereof, and a copolymer of two or more of these materials.

Further, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is separately formed and the scan line driver circuit 4004 or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013. A terminal electrode 4016 is formed using the same conductive film as source and drain electrode layers of the transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 via an anisotropic conductive film 4019.

Note that FIGS. 11A1, 11A2, and 11B illustrate the example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 12 illustrates an example of a liquid crystal display module which is formed as a semiconductor device using a transistor substrate 2600 to which the transistors described in Embodiment 1 are applied.

FIG. 12 illustrates an example of the liquid crystal display module, in which the transistor substrate 2600 and a counter substrate 2601 are bonded to each other with a sealant 2602, and a pixel portion 2603 including a transistor and the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and the like are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the RGB system, coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are provided outside the transistor substrate 2600 and the counter substrate 2601. A light source includes a cold cathode tube 2610 and a reflective plate 2611. A circuit board 2612 is connected to a wiring circuit portion 2608 of the transistor substrate 2600 by a flexible wiring board 2609 and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be employed.

Through the above process, a highly reliable liquid crystal display panel as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 7)

In this embodiment, an example of electronic paper is described as a semiconductor device to which the transistors described in Embodiment 1 are applied.

FIG. 13 illustrates active matrix electronic paper as an example of a semiconductor device. The transistor described in Embodiment 1 can be used as a transistor 581 used for the semiconductor device. The transistor described in Embodiments 1 can be used as a transistor 581 used for the semiconductor device.

The electronic paper in FIG. 13 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The transistor 581 sealed between a substrate 580 and a substrate 596 is a transistor which is one embodiment of the present invention, and a source electrode layer and a drain electrode layer thereof is in contact with a first electrode layer 587 at an opening formed in insulating layers 583 and 585, whereby the transistor 581 is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and a second electrode layer 588, spherical particles 589 each having a black region 590 a, a white region 590 b, and a cavity 594 around the regions, which is filled with liquid, are provided. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 13). The cavity 594 in the spherical particle 589 is filled with liquid, and also includes a particle having the black region 590 a and the white region 590 b. In this embodiment, the first electrode layer 587 and the second electrode layer 588 correspond to a pixel electrode and a common electrode, respectively. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the transistor 581. With the use of any one of the common connection portions described in Embodiment 1, the second electrode layer 588 and the common potential line can be electrically connected to each other through conductive particles provided between the pair of substrates.

Further, instead of the twisting ball, an electrophoretic element may be used. A microcapsule having a diameter approximately more than or equal to 10 μm and less than or equal to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and black microparticles move to opposite sides from each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is generally called electronic paper. The electrophoretic display element has a higher reflectivity than a liquid crystal display element and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to as a display device simply or a semiconductor device provided with a display device) is distanced from a radio wave source.

Through the above process, highly reliable electronic paper as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 8)

In this embodiment, an example of a light-emitting display device will be described as a semiconductor device to which the transistors described in Embodiment 1 are applied. A light-emitting element utilizing electroluminescence will be described here as a display element included in the display device. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, the carriers (electrons and holes) recombine, so that the light-emitting organic compound is excited. Then, light emission is caused when the light-emitting organic compound returns to a ground state from the excited state. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission which utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is arranged between dielectric layers, which are further arranged between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made in this embodiment using an organic EL element as a light-emitting element.

FIG. 14 illustrates an example of a pixel configuration to which digital time grayscale driving can be applied as an example of the semiconductor device to which the present invention is applied. Note that the term “OS” in the drawing indicates a thin film transistor in which an oxide semiconductor is used.

The configuration and operation of a pixel to which digital time grayscale driving can be applied will be described. An example is described here in which one pixel includes two n-channel transistors described in Embodiment 1, in each of which an oxide semiconductor layer (an In—Ga—Zn—O-based film) is used for a channel formation region.

A pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. In the switching transistor 6401, a gate thereof is connected to a scan line 6406, a first electrode thereof (one of source and drain electrodes) is connected to a signal line 6405, and a second electrode thereof (the other of the source and drain electrodes) is connected to a gate of the driving transistor 6402. In the driving transistor 6402, the gate thereof is connected to a power supply line 6407 through the capacitor 6403, a first electrode thereof is connected to the power supply line 6407, and a second electrode thereof is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line provided over the same substrate, and the connection portion may be used as a common connection portion.

Note that the second electrode (common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential with reference to the high power supply potential that is set on the power supply line 6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. The difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 so that current flows through the light-emitting element 6404, whereby the light-emitting element 6404 emits light. Thus, each potential is set so that the difference between the high power supply potential and the low power supply potential is greater than or equal to a forward threshold voltage of the light-emitting element 6404.

When the gate capacitance of the driving transistor 6402 is used as a substitute for the capacitor 6403, the capacitor 6403 can be omitted. The gate capacitance of the driving transistor 6402 may be formed between the channel region and the gate electrode.

In the case of using a voltage-input voltage driving method, a video signal is input to the gate of the driving transistor 6402 so that the driving transistor 6402 is in either of two states of being sufficiently turned on and turned off. That is, the driving transistor 6402 operates in a linear region. A voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402 so that the driving transistor 6402 operates in a linear region. Note that a voltage higher than or equal to the following is applied to the signal line 6405: power supply line voltage+V_(th) of the driving transistor 6402.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel configuration as FIG. 14 can be employed by changing signal input.

In the case of performing analog grayscale driving, voltage higher than or equal to the following is applied to the gate of the driving transistor 6402: forward voltage of the light-emitting element 6404+V_(th) of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to voltage to obtain a desired luminance, and includes at least forward threshold voltage. By input of a video signal which enables the driving transistor 6402 to operate in a saturation region, it is possible to feed current to the light-emitting element 6404. In order that the driving transistor 6402 can operate in the saturation region, the potential of the power supply line 6407 is set higher than a gate potential of the driving transistor 6402. When an analog video signal is used, it is possible to feed current to the light-emitting element 6404 in accordance with the video signal and perform analog grayscale driving.

Note that the pixel configuration is not limited to that illustrated in FIG. 14. For example, the pixel illustrated in FIG. 14 may further include a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like.

Next, structures of the light-emitting element will be described with reference to FIGS. 15A to 15C. A cross-sectional structure of a pixel will be described by taking an n-channel driving transistor as an example. A transistor 7011, a transistor 7021, and a transistor 7001 which are driving transistors used for semiconductor devices illustrated in FIGS. 15A, 15B, and 15C, respectively, can be manufactured in a manner similar to that of the transistor described in Embodiment 1, and are highly reliable transistors each including an In—Ga—Zn—O-based film as an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to transmit light. A transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure in which light is extracted through the surface opposite to the substrate, a bottom emission structure in which light is extracted through the surface on the substrate side, or a dual emission structure in which light is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel configuration of the present invention can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a bottom emission structure will be described with reference to FIG. 15A.

FIG. 15A is a cross-sectional view of a pixel in the case where the driving transistor 7011 is of an n-type and light is emitted from a light-emitting element 7012 to a first electrode 7013 side. In FIG. 15A, the first electrode 7013 of the light-emitting element 7012 is formed over a conductive film 7017 having a light-transmitting property with respect to visible light which is electrically connected to a drain electrode layer of the driving transistor 7011, and an EL layer 7014 and a second electrode 7015 are stacked in that order over the first electrode 7013.

As the conductive film 7017 having a light-transmitting property with respect to visible light, a conductive film having a light-transmitting property with respect to visible light such as a film of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode 7013 of the light-emitting element can be formed using various materials. For example, in the case where the first electrode 7013 is used as a cathode, a material having a low work function, for example, an alkali metal such as Li or Cs, an alkaline-earth metal such as Mg, Ca, or Sr, an alloy containing any of these (Mg:Ag, Al:Li, or the like), a rare-earth metal such as Yb or Er, or the like, is preferably used. In FIG. 15A, the thickness of the first electrode 7013 is such that the first electrode transmits light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used for the first electrode 7013.

Note that the conductive film having a light-transmitting property with respect to visible light and the aluminum film may be stacked and then selectively etched, so that the conductive film 7017 having a light-transmitting property with respect to visible light and the first electrode 7013 may be formed. In this case, the etching can be performed using the same mask, which is preferable.

A partition 7019 is formed in the protective insulating layer 7035 and the insulating layer 7032 and over a contact hole which reaches the drain electrode layer, provided the conductive film 7017 therebetween. The peripheral portion of the first electrode 7013 may be covered with a partition. The partition 7019 is formed using an organic resin film such as polyimide, an acrylic resin, polyamide, or an epoxy resin, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition 7019 be formed using a photosensitive resin material to have an opening over the first electrode 7013 so that a sidewall of the opening is formed as an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition 7019, a step of forming a resist mask can be omitted.

The EL layer 7014 formed over the first electrode 7013 and the partition 7019 may be formed using a single layer or a plurality of layers stacked as long as it includes at least a light-emitting layer. When the EL layer 7014 is formed using a plurality of layers, the EL layer 7014 is formed by stacking an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer in that order over the first electrode 7013 functioning as a cathode. Note that not all of these layers need to be provided.

The stacking order is not limited to the above stacking order. The first electrode 7013 may function as an anode, and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in that order over the first electrode 7013. However, when power consumption is compared, it is preferable that the first electrode 7013 function as a cathode and an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in that order over the first electrode 7013, because an increase in voltage in the driver circuit portion can be suppressed and power consumption can be reduced.

As the second electrode 7015 formed over the EL layer 7014, various materials can be employed. For example, in the case where the second electrode 7015 is used as an anode, a material having a high work function (specifically, a work function higher than or equal to 4.0 eV), such as ZrN, Ti, W, Ni, Pt, or Cr; or a light-transmitting conductive material such as ITO, IZO, or ZnO is preferably used. A light-blocking film 7016 is formed over the second electrode 7015 using, for example, a metal which blocks light, a metal which reflects light, or the like. In this embodiment, an ITO film is used for the second electrode 7015, and a Ti film is used for the light-blocking film 7016.

The light-emitting element 7012 corresponds to a region where the EL layer 7014 including a light-transmitting layer is provided between the first electrode 7013 and the second electrode 7015. In the case of the element structure illustrated in FIG. 15A, light is emitted from the light-emitting element 7012 to the first electrode 7013 side as indicated by an arrow.

Note that in FIG. 15A, light emitted from the light-emitting element 7012 passes through a color filter layer 7033, an insulating layer 7032, an oxide insulating layer 7031, a gate insulating layer 7030, and a substrate 7010 and then is emitted.

The color filter layer 7033 is formed by a droplet discharge method such as an ink-jet method, a printing method, an etching method with the use of a photolithography technique, or the like.

The color filter layer 7033 is covered with an overcoat layer 7034, and also covered with a protective insulating layer 7035. Note that the overcoat layer 7034 having a thin thickness is illustrated in FIG. 15A; however, the overcoat layer 7034 is formed using a resin material such as an acrylic resin and has a function of planarizing a surface having unevenness due to the color filter layer 7033.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. 15B.

In FIG. 15B, a first electrode 7023 of a light-emitting element 7022 is formed over a conductive film 7027 having a light-transmitting property with respect to visible light which is electrically connected to a drain electrode layer of the driving transistor 7021, and an EL layer 7024 and a second electrode 7025 are stacked in that order over the first electrode 7023.

For the conductive film 7027 having a light-transmitting property with respect to visible light, a conductive film having a light-transmitting property with respect to visible light of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

The first electrode 7023 can be formed using various materials. For example, in the case where the first electrode 7023 is used as a cathode, a material having a low work function (specifically, less than or equal to 3.8 eV), an alkali metal such as Li or Cs; an alkaline-earth metal such as Mg, Ca, or Sr; an alloy containing any of these (Mg:Ag, Al:Li, or the like); a rare-earth metal such as Yb or Er; or the like is preferable. In this embodiment, the first electrode 7023 is used as a cathode and the first electrode 7023 is formed to a thickness such that the first electrode 7023 can transmit visible light (preferably, approximately 5 nm to 30 nm). For example, a 20-nm-thick aluminum film is used as the cathode.

Note that the conductive film having a light-transmitting property with respect to visible light and the aluminum film may be stacked and then selectively etched, so that the conductive film 7027 having a light-transmitting property with respect to visible light and the first electrode 7023 may be formed. In that case, etching can be performed with the use of the same mask, which is preferable.

A partition 7029 is formed in the protective insulating layer 7045 and the insulating layer 7042 and over a contact hole which reaches the drain electrode layer, provided the conductive film 7027 therebetween. The periphery of the first electrode 7023 may be covered with a partition. The partition 7029 is formed using an organic resin film such as polyimide, an acrylic resin, polyamide, or an epoxy resin; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition 7029 be formed using a photosensitive resin material to have an opening over the first electrode 7023 so that a sidewall of the opening is formed as an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition 7029, a step of forming a resist mask can be omitted.

The EL layer 7024 formed over the first electrode 7023 and the partition 7029 may be formed using either a single layer or a plurality of layers stacked as long as it includes at least a light-emitting layer. When the EL layer 7024 is formed using a plurality of layers, the EL layer 7024 is formed by stacking an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer in that order over the first electrode 7023 functioning as a cathode. Note that not all of these layers need to be provided.

The stacking order is not limited to the above. The first electrode 7023 may be used as an anode, and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in that order over the anode. However, for lower power consumption, it is preferable that the first electrode 7023 be used as a cathode and an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in this order over the cathode.

In addition, the second electrode 7025 formed over the EL layer 7024 can be formed using a variety of materials. For example, when the second electrode 7025 is used as an anode, a material with a high work function or a transparent conductive material such as ITO, IZO, or ZnO is preferable. In this embodiment, the second electrode 7025 is formed using an ITO film including silicon oxide and is used as an anode.

The light-emitting element 7022 corresponds to a region where the EL layer 7024 including a light-emitting layer is provided between the first electrode 7023 and the second electrode 7025. In the case of the element structure illustrated in FIG. 15B, light emitted from the light-emitting element 7022 is emitted to both the second electrode 7025 side and the first electrode 7023 side as indicated by arrows.

Note that in FIG. 15B, light emitted from the light-emitting element 7022 to the first electrode 7023 side passes through a color filter layer 7043, an insulating layer 7042, an oxide insulating layer 7041, a gate insulating layer 7040, and a substrate 7020 and then is emitted.

The color filter layer 7043 is formed by a droplet discharge method such as an ink-jet method, a printing method, an etching method with the use of a photolithography technique, or the like.

The color filter layer 7043 is covered with an overcoat layer 7044, and also covered with a protective insulating layer 7045.

Note that when a light-emitting element having a dual emission structure is used and full color display is performed on both display surfaces, light from the second electrode 7025 side does not pass through the color filter layer 7043; therefore, a sealing substrate provided with another color filter layer is preferably provided over the second electrode 7025.

Next, a light-emitting element having a top emission structure is described with reference to FIG. 15C.

FIG. 15C is a cross-sectional view of a pixel in the case where the transistor 7001, which is a driving transistor, is of n-type and light is emitted from a light-emitting element 7002 to a second electrode 7005 side. In FIG. 15C, a first electrode 7003 of the light-emitting element 7002 is formed to be electrically connected to the drain electrode layer of the driving transistor 7001, and an EL layer 7004 and the second electrode 7005 are stacked in that order over the first electrode 7003.

The first electrode 7003 can be formed using a variety of materials. For example, in the case where the first electrode 7003 is used as a cathode, a material having a low work function, for example, an alkali metal such as Li or Cs, an alkaline-earth metal such as Mg, Ca, or Sr, an alloy containing any of these (Mg:Ag, Al:Li, or the like), a rare-earth metal such as Yb or Er, or the like, is preferably used.

A partition 7009 is formed in the protective insulating layer 7052 and the insulating layer 7055 and over a contact hole which reaches the drain electrode layer, provided the conductive film 7003 therebetween. The periphery of the first electrode 7003 may be covered with a partition. The partition 7009 is formed using an organic resin film such as polyimide, an acrylic resin, polyamide, or an epoxy resin; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition 7009 be formed using a photosensitive resin material to have an opening over the first electrode 7003 so that a sidewall of the opening is inclined with continuous curvature. When the partition 7009 is formed using a photosensitive resin material, a step of forming a resist mask can be omitted.

The EL layer 7004 formed over the first electrode 7003 and the partition 7009 may be formed using either a single layer or a plurality of layers stacked as long as it includes at least a light-emitting layer. When the EL layer 7004 is formed using a plurality of layers, the EL layer 7004 is formed by stacking an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer in that order over the first electrode 7003 used as a cathode. Note that not all of these layers need to be provided.

The stacking order is not limited to the above stacking order, and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in that order over the first electrode 7003 used as an anode.

In FIG. 15C, a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer are stacked in that order over a stacked film in which a Ti film, an aluminum film, and a Ti film are stacked in that order, and thereover, a stacked layer of a Mg:Ag alloy thin film and ITO is formed.

However, in the case where the transistor 7001 is of an n-type, it is preferable that an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in that order over the first electrode 7003, because an increase in voltage in the driver circuit can be suppressed and power consumption can be reduced.

The second electrode 7005 is formed using a conductive material having a light-transmitting property with respect to visible light, and for example, a conductive film having a light-transmitting property with respect to visible light of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

The light-emitting element 7002 corresponds to a region where the EL layer 7004 is provided between the first electrode 7003 and the second electrode 7005. In the case of the pixel illustrated in FIG. 15C, light is emitted from the light-emitting element 7002 to the second electrode 7005 side as indicated by an arrow.

In FIG. 15C, the drain electrode layer of the transistor 7001 is electrically connected to the first electrode 7003 through a contact hole provided in an oxide insulating layer 7051, a protective insulating layer 7052, and an insulating layer 7055. A planarizing insulating layer 7053 can be formed using a resin material such as polyimide, an acrylic resin, benzocyclobutene, polyamide, or an epoxy resin. In addition to such resin materials, it is also possible to use a low-dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed of these materials. There is no particular limitation on the method for forming the planarization insulating layer 7053, and the planarization insulating layer 7053 can be formed, depending on the material, using a method such as a sputtering method, an SOG method, spin coating, dip coating, spray coating, or a droplet discharge method (such as an inkjet method, screen printing, offset printing, or the like), or a tool (equipment) such as a doctor knife, a roll coater, a curtain coater, or a knife coater.

In the structure of FIG. 15C, when full color display is performed, for example, the light-emitting element 7002 is used as a green light-emitting element, one of adjacent light-emitting elements is used as a red light-emitting element, and the other is used as a blue light-emitting element. Alternatively, a light-emitting display device capable of full color display may be manufactured using four kinds of light-emitting elements, which include white light-emitting elements in addition to three kinds of light-emitting elements.

In the structure of FIG. 15C, a light-emitting display device capable of full color display may be manufactured in such a way that all of a plurality of light-emitting elements which is arranged is white light-emitting elements and a sealing substrate having a color filter or the like is arranged on the light-emitting element 7002. A material which exhibits light of a single color such as white can be formed and combined with a color filter or a color conversion layer, whereby full color display can be performed.

Needless to say, display of monochromatic light can also be performed. For example, a lighting device may be formed with the use of white light emission, or an area-color light-emitting device may be formed with the use of a single color light emission.

If necessary, an optical film such as a polarizing film including a circularly polarizing plate may be provided.

Although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that the example is described in which a transistor which controls the driving of a light-emitting element (a driving transistor) is electrically connected to the light-emitting element; however, a structure may be employed in which a transistor for current control is connected between the driving transistor and the light-emitting element.

A semiconductor device described in this embodiment is not limited to the structures illustrated in FIGS. 15A to 15C and can be modified in various ways based on the technical spirit of the present invention.

Next, the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel) which is an embodiment of a semiconductor device to which the transistors described in Embodiment 1 are applied will be described with reference to FIGS. 16A and 16B. FIG. 16A is a plan view of a panel in which a transistor and a light-emitting element are sealed between a first substrate and a second substrate with a sealant. FIG. 16B is a cross-sectional view taken along line H-I of FIG. 16A.

A sealant 4505 is provided to surround a pixel portion 4502, a signal line driver circuit 4503 a, a signal line driver circuit 4503 b, a scan line driver circuit 4504 a, and a scan line driver circuit 4504 b, which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a display device be thus packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the display device is not exposed to the outside air.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b formed over the first substrate 4501 each include a plurality of transistors, and a transistor 4510 included in the pixel portion 4502 and a transistor 4509 included in the signal line driver circuit 4503 a are illustrated as an example in FIG. 16B.

For each of the transistors 4509 and 4510, the highly reliable transistor described in Embodiment 1 which includes an In—Ga—Zn—O-based film as an oxide semiconductor layer can be applied. In this embodiment, the transistors 4509 and 4510 are n-channel transistors.

A conductive layer 4540 is provided over an insulating layer 4544 in a portion which overlaps with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the driver circuit. When the conductive layer 4540 is provided in a portion which overlaps with the channel formation region of the oxide semiconductor layer, the amount of shift in the threshold voltage of the transistor 4509 between before and after a BT test can be reduced. The conductive layer 4540 may have a potential which is the same as or different from that of the gate electrode layer of the transistor 4509, and can function as a second gate electrode layer. The potential of the conductive layer 4540 may be GND, 0 V or in a floating state.

Reference numeral 4511 denotes a light-emitting element, and a first electrode layer 4517 that is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to the structure described in this embodiment, which includes the first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

A partition 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition 4520 be formed of a photosensitive material to have an opening over the first electrode layer 4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 4512 may be formed using a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition 4520 in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC (diamond-like carbon) film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503 a and 4503 b, the scan line driver circuits 4504 a and 4504 b, or the pixel portion 4502 from an FPC 4518 a and an FPC 4518 b.

In this embodiment, a connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511, and a terminal electrode 4516 is formed from the same conductive film as the source and drain electrode layers included in the transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518 a through an anisotropic conductive film 4519.

The substrate located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property with respect to visible light. In that case, a material having a light-transmitting property with respect to visible light such as a glass plate, a plastic plate, a polyester film, or an acrylic resin film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler.

In addition, if needed, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan line driver circuits 4504 a and 4504 b may be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. Alternatively, only the signal line driver circuits or part thereof, or only the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 16A and 16B.

Through the above process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 9)

A semiconductor device to which the transistors described in Embodiment 1 are applied can be used as electronic paper. Electronic paper can be used for electronic devices of a variety of fields as long as they can display data. For example, electronic paper can be applied to an electronic book reader (e-book), a poster, an advertisement in a vehicle such as a train, displays of various cards such as a credit card, and the like. Examples of the electronic devices are illustrated in FIGS. 17A and 17B and FIG. 18.

FIG. 17A illustrates a poster 2631 formed using electronic paper. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time. Further, an image can be stably displayed without display deterioration. Note that the poster may have a configuration capable of wirelessly transmitting and receiving data.

FIG. 17B illustrates an advertisement 2632 in a vehicle such as a train. In the case where an advertising medium is printed paper, the advertisement is replaced by manpower; however, by using electronic paper, the advertising display can be changed in a short time without a lot of manpower. Further an image can be stably displayed without display deterioration. Note that the advertisement in a vehicle may have a configuration capable of wirelessly transmitting and receiving data.

FIG. 18 illustrates an example of an electronic book reader. For example, an electronic book reader 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are combined with a hinge 2711 so that the electronic book reader 2700 can be opened and closed with the hinge 2711 as an axis. With such a structure, the electronic book reader 2700 can be operated like a paper book.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, a display portion on the right side (the display portion 2705 in FIG. 18) can display text and a display portion on the left side (the display portion 2707 in FIG. 18) can display graphics.

FIG. 18 illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power switch 2721, an operation key 2723, a speaker 2725, and the like. With the operation key 2723, pages can be turned. Note that a keyboard, a pointing device, and the like may be provided on the same surface as the display portion of the housing. Further, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Further, the electronic book reader 2700 may have a function of an electronic dictionary.

The electronic book reader 2700 may have a configuration capable of wirelessly transmitting and receiving data. A structure may be employed in which a desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 10)

The semiconductor device including the transistors described in Embodiment 1 can be applied to a variety of electronic devices (including game machines). Examples of such electronic devices are a television device (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game console, a portable information terminal, an audio playback device, a large-sized game machine such as a pinball machine, and the like.

FIG. 19A illustrates an example of a television device. In a television device 9600, a display portion 9603 is incorporated in a housing 9601. The display portion 9603 can display images. Here, the housing 9601 is supported by a stand 9605.

The television device 9600 can be operated with an operation switch of the housing 9601 or a separate remote controller 9610. Channels can be switched and volume can be controlled with operation keys 9609 of the remote controller 9610, whereby an image displayed on the display portion 9603 can be controlled. Moreover, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.

Note that the television device 9600 is provided with a receiver, a modem, and the like. With the receiver, general TV broadcasts can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (e.g., between a sender and a receiver or between receivers) information communication can be performed.

FIG. 19B illustrates an example of a digital photo frame. For example, in a digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display a variety of images. For example, the display portion 9703 can display image data taken with a digital camera or the like and function as a normal photo frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection terminal (a USB terminal, a terminal connectable to a variety of cables such as a USB cable), a recording medium insertion portion, and the like. Although these components may be provided on the same surface as the display portion, it is preferable to provide them on the side surface or the back surface for design aesthetics. For example, a memory that stores image data taken with a digital camera is inserted into the recording medium insertion portion of the digital photo frame 9700 and the data is loaded, whereby the image can be displayed on the display portion 9703.

The digital photo frame 9700 may be configured to transmit and receive data wirelessly. Through wireless communication, desired image data can be loaded to be displayed.

FIG. 20A illustrates a portable game console including two housings, a housing 9881 and a housing 9891 which are jointed with a joint portion 9893 so that the portable game console can be opened or folded. A display portion 9882 and a display portion 9883 are incorporated in the housing 9881 and the housing 9891, respectively. In addition, the portable game console illustrated in FIG. 20A is provided with a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, smell, or infrared ray), and a microphone 9889), and the like. Needless to say, the structure of the portable game console is not limited to the above and another structure which is provided with at least a semiconductor device according to the present invention can be employed. The portable game console may include an additional accessory as appropriate. The portable game console illustrated in FIG. 20A has a function of reading a program or data stored in a recording medium to display it on the display portion, and a function of sharing data with another portable game console via wireless communication. Note that a function of the portable game console illustrated in FIG. 20A is not limited to those described above, and the portable game console can have a variety of functions.

FIG. 20B illustrates an example of a slot machine which is a large-sized game machine. In a slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. Needless to say, the structure of the slot machine 9900 is not limited to the above and another structure which is provided with at least the semiconductor device according to the present invention may be employed. The slot machine 9900 may include an additional accessory as appropriate.

FIG. 21A illustrates an example of a mobile phone. A mobile phone 1000 includes a housing 1001 in which a display portion 1002 is incorporated, an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

Information can be input to the mobile phone 1000 illustrated in FIG. 21A by touching the display portion 1002 with a finger or the like. Moreover, users can make a call or write an e-mail by touching the display portion 1002 with their fingers or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying images. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are combined.

For example, in the case of making a call or writing an e-mail, the display portion 1002 may be placed into a text input mode mainly for inputting text, and characters displayed on a screen can be input. In this case, it is preferable to display a keyboard or number buttons on almost the entire area of the screen of the display portion 1002.

When a detection device including a sensor which detects inclination, such as a gyroscope or an acceleration sensor, is provided inside the mobile phone 1000, display on the screen of the display portion 1002 can be automatically switched by detecting the direction of the mobile phone 1000 (whether the mobile phone 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

Further, the screen modes are switched by touching the display portion 1002 or operating the operation button 1003 of the housing 1001. Alternatively, the screen modes can be switched depending on the kinds of image displayed on the display portion 1002. For example, when a signal for an image displayed on the display portion is data of moving images, the screen mode is switched to the display mode. When the signal is text data, the screen mode is switched to the input mode.

Further, in the input mode, a signal is detected by an optical sensor in the display portion 1002 and if input by touching the display portion 1002 is not performed for a certain period, the screen mode may be controlled so as to be switched from the input mode to the display mode.

The display portion 1002 can also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when the display portion 1002 is touched with the palm or the finger, whereby personal authentication can be performed. Moreover, when a backlight or sensing light source which emits near-infrared light is provided in the display portion, an image of finger veins, palm veins, or the like can be taken.

FIG. 21B illustrates another example of a mobile phone. The mobile phone in FIG. 21B has a display device 9410 provided with a housing 9411 including a display portion 9412 and operation buttons 9413, and a communication device 9400 provided with a housing 9401 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting portion 9406 that emits light when a phone call is received. The display device 9410 having a display function can be detachably attached to the communication device 9400 having a phone function in two directions represented by the arrows. Thus, the display device 9410 and the communication device 9400 can be attached to each other along their short sides or long sides. In addition, when only the display function is needed, the display device 9410 can be detached from the communication device 9400 and used alone. Images or input information can be transmitted or received by wireless or wire communication between the communication device 9400 and the display device 9410, each of which has a rechargeable battery.

Note that the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

This application is based on Japanese Patent Application serial no. 2009-255535 filed with Japan Patent Office on Nov. 6, 2009, the entire contents of which are hereby incorporated by reference. 

The invention claimed is:
 1. A semiconductor device comprising: an inverter comprising a first transistor and a second transistor over a substrate, each of the first transistor and the second transistor comprising: a first electrode layer; an oxide semiconductor layer with a first insulating film interposed therebetween, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin; a second electrode layer on the oxide semiconductor layer; a third electrode layer on the oxide semiconductor layer; and a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and a second insulating film interposed therebetween, wherein the third electrode layer of the first transistor is electrically connected to the second electrode layer of the second transistor, wherein one of the first electrode layer and the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor, and wherein the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer over the first semiconductor layer.
 2. The semiconductor device according to claim 1, wherein a voltage is applied to the first electrode layer of the first transistor, the fourth electrode layer of the first transistor, and the first electrode layer and the fourth electrode layer of the second transistor respectively.
 3. The semiconductor device according to claim 1, wherein the first transistor is an enhancement transistor and the second transistor is a depletion transistor.
 4. The semiconductor device according to claim 1, wherein the fourth electrode layer is a main gate electrode in the first transistor, and wherein the fourth electrode layer is a main gate electrode in the second transistor.
 5. The semiconductor device according to claim 1, wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.
 6. The semiconductor device according to claim 1, wherein the first transistor has a different threshold value from the second transistor.
 7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor have the same composition and the same purity.
 8. The semiconductor device according to claim 1, wherein the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor.
 9. An electronic device comprising the semiconductor device according to claim
 1. 10. A semiconductor device comprising: an inverter comprising a first transistor and a second transistor over a substrate, each of the first transistor and the second transistor comprising: a first electrode layer; an oxide semiconductor layer with a first insulating film interposed therebetween, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin; a second electrode layer on the oxide semiconductor layer; a third electrode layer on the oxide semiconductor layer; and a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and a second insulating film interposed therebetween, wherein the third electrode layer of the first transistor is electrically connected to the second electrode layer of the second transistor, wherein one of the first electrode layer and the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor, wherein the oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer over the first semiconductor layer, wherein the second oxide semiconductor layer comprises a crystalline region comprising crystals, and wherein c-axes of the crystals are oriented substantially in a direction perpendicular to a surface of the oxide semiconductor layer.
 11. The semiconductor device according to claim 10, wherein a voltage is applied to the first electrode layer of the first transistor, the fourth electrode layer of the first transistor, and the first electrode layer and the fourth electrode layer of the second transistor respectively.
 12. The semiconductor device according to claim 10, wherein the first transistor is an enhancement transistor and the second transistor is a depletion transistor.
 13. The semiconductor device according to claim 10, wherein the fourth electrode layer is a main gate electrode in the first transistor, and wherein the fourth electrode layer is a main gate electrode in the second transistor.
 14. The semiconductor device according to claim 10, wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.
 15. The semiconductor device according to claim 10, wherein the first transistor has a different threshold value from the second transistor.
 16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer of the first transistor and the oxide semiconductor layer of the second transistor have the same composition and the same purity.
 17. The semiconductor device according to claim 10, wherein the fourth electrode layer of the second transistor is electrically connected to the second electrode layer of the second transistor.
 18. An electronic device comprising the semiconductor device according to claim
 10. 